Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2008178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37174677

1

T1

11740

T2

14650

T3

115261

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27429775	1			T1	5099		T2	6408		T3	102259
values[0x0]	10264295	1			T1	6641		T2	8242		T3	13002
values[0x1]	1488785	1			T1	890		T2	1113		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	681351	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38501504

1

T1

12630

T2

15763

T3

115268

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18378787	1			T1	6316		T2	7882		T3	57634
valid_sources[0x01]	18379260	1			T1	6314		T2	7881		T3	57634
valid_sources[0x02]	38340	1			T384	81		T548	15		T151	168
valid_sources[0x03]	39293	1			T51	1		T384	95		T548	13
valid_sources[0x04]	39591	1			T79	39		T150	3		T384	89
valid_sources[0x05]	39380	1			T224	1		T150	1		T384	92
valid_sources[0x06]	39036	1			T150	1		T384	82		T548	14
valid_sources[0x07]	38765	1			T257	5		T384	81		T548	21
valid_sources[0x08]	38602	1			T384	57		T548	23		T151	146
valid_sources[0x09]	38955	1			T257	6		T150	2		T384	88
valid_sources[0x0a]	38352	1			T150	1		T384	72		T548	19
valid_sources[0x0b]	39280	1			T384	88		T548	16		T151	181
valid_sources[0x0c]	39782	1			T224	1		T384	85		T548	15
valid_sources[0x0d]	43716	1			T257	3		T150	1		T384	85
valid_sources[0x0e]	38893	1			T51	3		T384	98		T548	17
valid_sources[0x0f]	37840	1			T150	3		T384	83		T548	20
valid_sources[0x10]	39396	1			T150	1		T384	78		T548	16
valid_sources[0x11]	38209	1			T51	1		T384	70		T548	21
valid_sources[0x12]	38359	1			T51	2		T80	4		T384	112
valid_sources[0x13]	38843	1			T51	6		T257	4		T384	72
valid_sources[0x14]	38963	1			T51	4		T150	2		T384	104
valid_sources[0x15]	40156	1			T384	81		T548	19		T151	173
valid_sources[0x16]	38652	1			T150	1		T384	74		T548	18
valid_sources[0x17]	38304	1			T80	3		T224	4		T150	1
valid_sources[0x18]	39229	1			T257	1		T224	1		T384	98
valid_sources[0x19]	39425	1			T384	70		T548	17		T151	220
valid_sources[0x1a]	38360	1			T51	1		T80	5		T384	109
valid_sources[0x1b]	39440	1			T224	1		T150	1		T384	87
valid_sources[0x1c]	40215	1			T51	2		T384	107		T548	18
valid_sources[0x1d]	38862	1			T224	1		T384	71		T548	15
valid_sources[0x1e]	39955	1			T51	2		T80	5		T384	92
valid_sources[0x1f]	38002	1			T80	6		T150	2		T384	82
valid_sources[0x20]	38798	1			T257	3		T384	87		T548	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26702775

1

T1

5099

T2

6408

T3

102259

values[0x0]

all_enables

biggest_size

10200535

1

T1

6641

T2

8242

T3

13002

values[0x1]

all_enables

biggest_size

271367

1

T79

22

T51

22

T80

14

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2959102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

467327

1

T75

134

T76

10

T77

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1159692	1			T75	564		T76	25		T77	37
values[0x0]	1105845	1			T75	107		T76	26		T77	29
values[0x1]	1160892	1			T75	556		T76	26		T77	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2291039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1135390

1

T75

471

T76

21

T77

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53641	1			T75	13		T76	1		T81	1
valid_sources[0x01]	53086	1			T75	22		T76	1		T77	1
valid_sources[0x02]	53235	1			T75	16		T81	12		T313	13
valid_sources[0x03]	53408	1			T75	14		T76	1		T77	2
valid_sources[0x04]	53878	1			T75	16		T76	3		T77	1
valid_sources[0x05]	53114	1			T75	21		T76	2		T77	1
valid_sources[0x06]	52508	1			T75	18		T76	4		T81	40
valid_sources[0x07]	53965	1			T75	12		T76	10		T77	7
valid_sources[0x08]	54522	1			T75	20		T77	2		T81	7
valid_sources[0x09]	53886	1			T75	6		T81	1		T313	9
valid_sources[0x0a]	54776	1			T75	20		T77	5		T81	21
valid_sources[0x0b]	53657	1			T75	23		T76	1		T81	20
valid_sources[0x0c]	53989	1			T75	28		T313	1		T130	318
valid_sources[0x0d]	53289	1			T75	23		T81	7		T313	9
valid_sources[0x0e]	53573	1			T75	22		T76	1		T77	4
valid_sources[0x0f]	53738	1			T75	16		T313	5		T130	356
valid_sources[0x10]	54286	1			T75	24		T81	5		T313	3
valid_sources[0x11]	52712	1			T75	15		T76	1		T77	4
valid_sources[0x12]	53498	1			T75	14		T81	6		T313	3
valid_sources[0x13]	54343	1			T75	21		T76	2		T77	2
valid_sources[0x14]	53900	1			T75	18		T81	6		T313	9
valid_sources[0x15]	53532	1			T75	28		T77	2		T81	27
valid_sources[0x16]	53524	1			T75	21		T81	21		T313	8
valid_sources[0x17]	53700	1			T75	25		T76	4		T81	1
valid_sources[0x18]	55349	1			T75	11		T76	1		T81	20
valid_sources[0x19]	53083	1			T75	19		T76	6		T77	1
valid_sources[0x1a]	53687	1			T75	15		T77	3		T81	21
valid_sources[0x1b]	52999	1			T75	19		T313	4		T130	349
valid_sources[0x1c]	52981	1			T75	16		T77	1		T81	5
valid_sources[0x1d]	53571	1			T75	22		T77	2		T81	31
valid_sources[0x1e]	53665	1			T75	18		T77	2		T81	24
valid_sources[0x1f]	54311	1			T75	13		T77	2		T313	2
valid_sources[0x20]	53413	1			T75	19		T76	2		T81	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49475

1

T75

50

T77

4

T81

12

values[0x0]

all_enables

biggest_size

368274

1

T75

38

T76

8

T77

11

values[0x1]

all_enables

biggest_size

49578

1

T75

46

T76

2

T77

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3142544	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

511537

1

T75

139

T76

17

T77

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1250828	1			T75	603		T76	50		T77	51
values[0x0]	1152021	1			T75	104		T76	45		T77	59
values[0x1]	1251232	1			T75	658		T76	51		T77	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2411060	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1243021

1

T75

517

T76

50

T77

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57617	1			T75	27		T76	2		T77	10
valid_sources[0x01]	56088	1			T75	26		T81	6		T313	7
valid_sources[0x02]	56558	1			T75	21		T76	2		T77	4
valid_sources[0x03]	56725	1			T75	34		T76	3		T77	4
valid_sources[0x04]	57092	1			T75	13		T76	1		T81	7
valid_sources[0x05]	56519	1			T75	19		T76	2		T77	11
valid_sources[0x06]	56294	1			T75	18		T76	6		T81	3
valid_sources[0x07]	57426	1			T75	17		T76	4		T81	8
valid_sources[0x08]	57394	1			T75	19		T76	7		T81	7
valid_sources[0x09]	58825	1			T75	15		T76	3		T77	22
valid_sources[0x0a]	57407	1			T75	15		T76	6		T81	7
valid_sources[0x0b]	56942	1			T75	24		T76	5		T81	12
valid_sources[0x0c]	56974	1			T75	28		T76	2		T77	16
valid_sources[0x0d]	57165	1			T75	15		T76	2		T77	2
valid_sources[0x0e]	57782	1			T75	17		T76	2		T77	7
valid_sources[0x0f]	55951	1			T75	16		T76	2		T81	10
valid_sources[0x10]	58296	1			T75	17		T76	3		T77	6
valid_sources[0x11]	57223	1			T75	27		T76	3		T81	7
valid_sources[0x12]	57488	1			T75	15		T76	1		T77	2
valid_sources[0x13]	56601	1			T75	25		T76	1		T77	1
valid_sources[0x14]	57160	1			T75	13		T76	2		T81	10
valid_sources[0x15]	56543	1			T75	22		T77	8		T81	8
valid_sources[0x16]	57186	1			T75	24		T76	5		T81	7
valid_sources[0x17]	57159	1			T75	26		T76	6		T77	13
valid_sources[0x18]	57299	1			T75	21		T76	1		T77	7
valid_sources[0x19]	57293	1			T75	21		T81	9		T313	5
valid_sources[0x1a]	57934	1			T75	15		T76	2		T77	4
valid_sources[0x1b]	57175	1			T75	24		T76	1		T81	11
valid_sources[0x1c]	57264	1			T75	33		T76	4		T81	8
valid_sources[0x1d]	57187	1			T75	31		T76	2		T81	10
valid_sources[0x1e]	57731	1			T75	22		T76	2		T77	1
valid_sources[0x1f]	57199	1			T75	10		T81	8		T313	4
valid_sources[0x20]	56806	1			T75	24		T76	1		T81	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53598

1

T75

40

T76

1

T77

2

values[0x0]

all_enables

biggest_size

404349

1

T75

49

T76

14

T77

20

values[0x1]

all_enables

biggest_size

53590

1

T75

50

T76

2

T77

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2986505	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

472408

1

T75

124

T76

5

T77

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1172597	1			T75	618		T76	20		T77	57
values[0x0]	1114672	1			T75	102		T76	17		T77	46
values[0x1]	1171644	1			T75	627		T76	25		T77	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2311101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1147812

1

T75

486

T76

17

T77

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54611	1			T75	24		T77	1		T81	10
valid_sources[0x01]	54138	1			T75	16		T77	5		T81	26
valid_sources[0x02]	53726	1			T75	24		T76	1		T77	2
valid_sources[0x03]	54238	1			T75	25		T76	1		T77	2
valid_sources[0x04]	54665	1			T75	17		T77	1		T81	9
valid_sources[0x05]	53413	1			T75	23		T76	1		T77	1
valid_sources[0x06]	53074	1			T75	15		T76	1		T77	3
valid_sources[0x07]	53753	1			T75	17		T81	14		T313	5
valid_sources[0x08]	53894	1			T75	21		T77	5		T81	6
valid_sources[0x09]	55363	1			T75	27		T77	4		T313	15
valid_sources[0x0a]	54395	1			T75	29		T77	4		T81	14
valid_sources[0x0b]	55086	1			T75	16		T76	2		T77	7
valid_sources[0x0c]	54388	1			T75	24		T76	3		T81	29
valid_sources[0x0d]	53872	1			T75	14		T77	3		T81	5
valid_sources[0x0e]	54833	1			T75	16		T77	6		T81	20
valid_sources[0x0f]	53930	1			T75	17		T76	5		T77	1
valid_sources[0x10]	54128	1			T75	34		T77	1		T81	36
valid_sources[0x11]	53470	1			T75	10		T77	1		T81	16
valid_sources[0x12]	54078	1			T75	28		T76	1		T77	1
valid_sources[0x13]	53959	1			T75	19		T76	1		T77	4
valid_sources[0x14]	53749	1			T75	26		T76	1		T77	3
valid_sources[0x15]	52848	1			T75	24		T77	2		T313	8
valid_sources[0x16]	53275	1			T75	23		T76	2		T77	3
valid_sources[0x17]	54242	1			T75	18		T77	1		T81	1
valid_sources[0x18]	53497	1			T75	21		T77	2		T81	4
valid_sources[0x19]	55118	1			T75	29		T77	5		T81	31
valid_sources[0x1a]	54070	1			T75	15		T77	1		T81	20
valid_sources[0x1b]	54017	1			T75	17		T81	12		T313	4
valid_sources[0x1c]	54483	1			T75	25		T77	5		T81	3
valid_sources[0x1d]	53602	1			T75	28		T77	3		T81	21
valid_sources[0x1e]	53935	1			T75	12		T77	2		T81	11
valid_sources[0x1f]	54986	1			T75	14		T77	6		T81	2
valid_sources[0x20]	53620	1			T75	37		T81	6		T313	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49978

1

T75

49

T77

4

T81

8

values[0x0]

all_enables

biggest_size

372808

1

T75

38

T76

5

T77

12

values[0x1]

all_enables

biggest_size

49622

1

T75

37

T77

3

T81

15