SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
0.00 | 0.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tb.dut.top_earlgrey.u_rv_core_ibex.u_core.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_prim_onehot_check_raddr_b.u_prim_onehot_check_if | 0.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 3 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_onehot_addr_fault | 1 | 1 | 0 | 0.00 | 100 | 1 | 1 | 0 | |
cp_onehot_enable_fault | 1 | 1 | 0 | 0.00 | 100 | 1 | 1 | 0 | |
cp_onehot_fault | 1 | 1 | 0 | 0.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 1 | 1 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
hit | 0 | 1 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 1 | 1 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
hit | 0 | 1 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 1 | 1 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
hit | 0 | 1 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |