Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : ibex_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.34 93.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core 95.66 95.66



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.66 95.66


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.66 95.66


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.50 95.29 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : ibex_top
TotalCoveredPercent
Totals 42 32 76.19
Total Bits 826 771 93.34
Total Bits 0->1 413 386 93.46
Total Bits 1->0 413 385 93.22

Ports 42 32 76.19
Port Bits 826 771 93.34
Port Bits 0->1 413 386 93.46
Port Bits 1->0 413 385 93.22

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T33 Yes T1,T2,T3 INPUT
test_en_i No No No INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
instr_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
instr_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
instr_addr_o[16:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
instr_addr_o[18:17] No No No OUTPUT
instr_addr_o[19] No No Yes T388,T389,T390 OUTPUT
instr_addr_o[27:20] No No No OUTPUT
instr_addr_o[29:28] Yes Yes *T43,*T246,*T263 Yes T43,T246,T262 OUTPUT
instr_addr_o[31:30] No No No OUTPUT
instr_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_err_i Yes Yes T95,T43,T67 Yes T95,T43,T67 INPUT
data_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_we_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_be_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
data_addr_o[31:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_intg_o[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_err_i Yes Yes T2,T62,T95 Yes T2,T62,T95 INPUT
irq_software_i Yes Yes T258,T259,T260 Yes T258,T259,T260 INPUT
irq_timer_i Yes Yes T159,T103,T261 Yes T159,T103,T261 INPUT
irq_external_i Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
irq_fast_i[14:0] Unreachable Unreachable Unreachable INPUT
irq_nm_i Yes Yes T2,T62,T95 Yes T2,T62,T95 INPUT
scramble_key_valid_i Yes Yes T185,T186,T188 Yes T185,T186,T188 INPUT
scramble_key_i[127:0] Yes Yes T2,T3,T34 Yes T2,T3,T34 INPUT
scramble_nonce_i[63:0] Yes Yes T2,T3,T34 Yes T2,T3,T34 INPUT
scramble_req_o Yes Yes T185,T186,T187 Yes T185,T186,T187 OUTPUT
debug_req_i Yes Yes T67,T262,T263 Yes T67,T262,T263 INPUT
crash_dump_o.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
double_fault_seen_o Yes Yes T247,T248,T249 Yes T247,T248,T249 OUTPUT
fetch_enable_i[3:0] Yes Yes T1,T2,T5 Yes T1,T2,T3 INPUT
alert_minor_o No No No OUTPUT
alert_major_internal_o No No No OUTPUT
alert_major_bus_o Yes Yes T182,T245,T246 Yes T182,T245,T246 OUTPUT
core_sleep_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core
TotalCoveredPercent
Totals 38 32 84.21
Total Bits 806 771 95.66
Total Bits 0->1 403 386 95.78
Total Bits 1->0 403 385 95.53

Ports 38 32 84.21
Port Bits 806 771 95.66
Port Bits 0->1 403 386 95.78
Port Bits 1->0 403 385 95.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T33 Yes T1,T2,T3 INPUT
test_en_i No No No INPUT
ram_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
instr_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
instr_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
instr_addr_o[16:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
instr_addr_o[18:17] No No No OUTPUT
instr_addr_o[19] No No Yes T388,T389,T390 OUTPUT
instr_addr_o[27:20] No No No OUTPUT
instr_addr_o[29:28] Yes Yes *T43,*T246,*T263 Yes T43,T246,T262 OUTPUT
instr_addr_o[31:30] No No No OUTPUT
instr_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_err_i Yes Yes T95,T43,T67 Yes T95,T43,T67 INPUT
data_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_we_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_be_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
data_addr_o[31:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_intg_o[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_err_i Yes Yes T2,T62,T95 Yes T2,T62,T95 INPUT
irq_software_i Yes Yes T258,T259,T260 Yes T258,T259,T260 INPUT
irq_timer_i Yes Yes T159,T103,T261 Yes T159,T103,T261 INPUT
irq_external_i Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
irq_fast_i[14:0] Unreachable Unreachable Unreachable INPUT
irq_nm_i Yes Yes T2,T62,T95 Yes T2,T62,T95 INPUT
scramble_key_valid_i Yes Yes T185,T186,T188 Yes T185,T186,T188 INPUT
scramble_key_i[127:0] Yes Yes T2,T3,T34 Yes T2,T3,T34 INPUT
scramble_nonce_i[63:0] Yes Yes T2,T3,T34 Yes T2,T3,T34 INPUT
scramble_req_o Yes Yes T185,T186,T187 Yes T185,T186,T187 OUTPUT
debug_req_i Yes Yes T67,T262,T263 Yes T67,T262,T263 INPUT
crash_dump_o.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
double_fault_seen_o Yes Yes T247,T248,T249 Yes T247,T248,T249 OUTPUT
fetch_enable_i[3:0] Yes Yes T1,T2,T5 Yes T1,T2,T3 INPUT
alert_minor_o No No No OUTPUT
alert_major_internal_o No No No OUTPUT
alert_major_bus_o Yes Yes T182,T245,T246 Yes T182,T245,T246 OUTPUT
core_sleep_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%