Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523355434	61083443	0	0
DepthKnown_A	523355434	523247588	0	0
RvalidKnown_A	523355434	523247588	0	0
WreadyKnown_A	523355434	523247588	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	61083443	0	0
T1	236116	21895	0	0
T2	247412	32301	0	0
T3	128142	142724	0	0
T4	153000	16017	0	0
T5	143938	19350	0	0
T34	101445	15315	0	0
T59	162522	21688	0	0
T86	56533	5340	0	0
T87	69572	6817	0	0
T88	74237	6692	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523355434	47021473	0	0
DepthKnown_A	523355434	523247588	0	0
RvalidKnown_A	523355434	523247588	0	0
WreadyKnown_A	523355434	523247588	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	47021473	0	0
T1	236116	17635	0	0
T2	247412	22727	0	0
T3	128142	123693	0	0
T4	153000	11930	0	0
T5	143938	14273	0	0
T34	101445	11023	0	0
T59	162522	16551	0	0
T86	56533	3579	0	0
T87	69572	5152	0	0
T88	74237	4693	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523355434	43584966	0	0
DepthKnown_A	523355434	523247588	0	0
RvalidKnown_A	523355434	523247588	0	0
WreadyKnown_A	523355434	523247588	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	43584966	0	0
T1	236116	12875	0	0
T2	247412	16145	0	0
T3	128142	174639	0	0
T4	153000	12049	0	0
T5	143938	8280	0	0
T34	101445	9621	0	0
T59	162522	9926	0	0
T86	56533	2934	0	0
T87	69572	4113	0	0
T88	74237	3716	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523355434	36774365	0	0
DepthKnown_A	523355434	523247588	0	0
RvalidKnown_A	523355434	523247588	0	0
WreadyKnown_A	523355434	523247588	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	36774365	0	0
T1	236116	12630	0	0
T2	247412	15763	0	0
T3	128142	115268	0	0
T4	153000	11777	0	0
T5	143938	8012	0	0
T34	101445	9406	0	0
T59	162522	9648	0	0
T86	56533	2819	0	0
T87	69572	3999	0	0
T88	74237	3573	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	523247588	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	600225659	100525	0	0
DepthKnown_A	600225659	600101703	0	0
RvalidKnown_A	600225659	600101703	0	0
WreadyKnown_A	600225659	600101703	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	100525	0	0
T1	236116	30	0	0
T2	247412	151	0	0
T3	128142	34	0	0
T4	153000	94	0	0
T5	143938	26	0	0
T34	101445	15	0	0
T59	162522	26	0	0
T86	56533	13	0	0
T87	69572	13	0	0
T88	74237	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	600225659	102410	0	0
DepthKnown_A	600225659	600101703	0	0
RvalidKnown_A	600225659	600101703	0	0
WreadyKnown_A	600225659	600101703	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	102410	0	0
T1	236116	30	0	0
T2	247412	151	0	0
T3	128142	34	0	0
T4	153000	94	0	0
T5	143938	26	0	0
T34	101445	15	0	0
T59	162522	26	0	0
T86	56533	13	0	0
T87	69572	13	0	0
T88	74237	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	600225659	52792	0	0
DepthKnown_A	600225659	600101703	0	0
RvalidKnown_A	600225659	600101703	0	0
WreadyKnown_A	600225659	600101703	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	52792	0	0
T1	236116	28	0	0
T2	247412	95	0	0
T3	128142	5	0	0
T4	153000	93	0	0
T5	143938	23	0	0
T34	101445	14	0	0
T59	162522	23	0	0
T86	56533	12	0	0
T87	69572	12	0	0
T88	74237	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	600225659	52792	0	0
DepthKnown_A	600225659	600101703	0	0
RvalidKnown_A	600225659	600101703	0	0
WreadyKnown_A	600225659	600101703	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	52792	0	0
T1	236116	28	0	0
T2	247412	95	0	0
T3	128142	5	0	0
T4	153000	93	0	0
T5	143938	23	0	0
T34	101445	14	0	0
T59	162522	23	0	0
T86	56533	12	0	0
T87	69572	12	0	0
T88	74237	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	600225659	47733	0	0
DepthKnown_A	600225659	600101703	0	0
RvalidKnown_A	600225659	600101703	0	0
WreadyKnown_A	600225659	600101703	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	47733	0	0
T1	236116	2	0	0
T2	247412	56	0	0
T3	128142	29	0	0
T4	153000	1	0	0
T5	143938	3	0	0
T34	101445	1	0	0
T59	162522	3	0	0
T86	56533	1	0	0
T87	69572	1	0	0
T88	74237	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	600225659	49618	0	0
DepthKnown_A	600225659	600101703	0	0
RvalidKnown_A	600225659	600101703	0	0
WreadyKnown_A	600225659	600101703	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	49618	0	0
T1	236116	2	0	0
T2	247412	56	0	0
T3	128142	29	0	0
T4	153000	1	0	0
T5	143938	3	0	0
T34	101445	1	0	0
T59	162522	3	0	0
T86	56533	1	0	0
T87	69572	1	0	0
T88	74237	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600225659	600101703	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0