Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.39	87.81		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.39	87.81		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.39	87.81		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.39	87.81		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T78	Yes	T67,T68,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T79,T51,T80	Yes	T79,T51,T80	INPUT
tl_i.a_valid	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	INPUT
tl_o.a_ready	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T263,*T731,*T264	Yes	T263,T731,T264	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T88,*T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T358,T164	Yes	T59,T358,T164	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T358,T164	Yes	T59,T358,T164	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T33	Yes	T1,T2,T34	INPUT
cio_tx_o	Yes	Yes	T3,T8,T43	Yes	T3,T8,T43	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T221,T216,T153	Yes	T221,T216,T153	OUTPUT
intr_tx_empty_o	Yes	Yes	T221,T216,T153	Yes	T221,T216,T153	OUTPUT
intr_rx_watermark_o	Yes	Yes	T221,T216,T153	Yes	T221,T216,T153	OUTPUT
intr_tx_done_o	Yes	Yes	T221,T216,T153	Yes	T221,T216,T153	OUTPUT
intr_rx_overflow_o	Yes	Yes	T221,T216,T153	Yes	T221,T216,T153	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_break_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_timeout_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T78	Yes	T67,T68,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T79,T51,T80	Yes	T79,T51,T80	INPUT
tl_i.a_valid	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	INPUT
tl_o.a_ready	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_error	Yes	Yes	T75,T77,T81	Yes	T75,T77,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T77,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T263,*T731,*T264	Yes	T263,T731,T264	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T81,T130	Yes	T75,T77,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T88,*T8	Yes	T3,T88,T8	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T88,T8	Yes	T3,T88,T8	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T358,T164,T83	Yes	T358,T164,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T358,T164,T83	Yes	T358,T164,T83	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T33	Yes	T1,T2,T34	INPUT
cio_tx_o	Yes	Yes	T3,T8,T43	Yes	T3,T8,T43	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T221,T222,T314	Yes	T221,T222,T314	OUTPUT
intr_tx_empty_o	Yes	Yes	T221,T222,T314	Yes	T221,T222,T314	OUTPUT
intr_rx_watermark_o	Yes	Yes	T221,T222,T314	Yes	T221,T222,T314	OUTPUT
intr_tx_done_o	Yes	Yes	T221,T222,T314	Yes	T221,T222,T314	OUTPUT
intr_rx_overflow_o	Yes	Yes	T221,T222,T314	Yes	T221,T222,T314	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_break_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_timeout_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T216,T314,T217	Yes	T216,T314,T217	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T216,T314,T217	Yes	T216,T314,T217	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T78	Yes	T67,T68,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T79,T51,T80	Yes	T79,T51,T80	INPUT
tl_i.a_valid	Yes	Yes	T164,T250,T216	Yes	T164,T250,T216	INPUT
tl_o.a_ready	Yes	Yes	T164,T250,T216	Yes	T164,T250,T216	OUTPUT
tl_o.d_error	Yes	Yes	T75,T77,T81	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T216,T314,T217	Yes	T216,T314,T217	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T164,T250,T216	Yes	T164,T250,T216	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T164,T250,T216	Yes	T164,T250,T216	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T224,*T150,*T75	Yes	T224,T150,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T216,*T314,*T217	Yes	T216,T314,T217	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T164,T250,T216	Yes	T164,T250,T216	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T164,T83	Yes	T59,T164,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T163	Yes	T83,T163,T451	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T163,T451	Yes	T83,T84,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T164,T83	Yes	T59,T164,T83	OUTPUT
cio_rx_i	Yes	Yes	T216,T217,T218	Yes	T216,T9,T10	INPUT
cio_tx_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T216,T314,T217	Yes	T216,T314,T217	OUTPUT
intr_tx_empty_o	Yes	Yes	T216,T314,T217	Yes	T216,T314,T217	OUTPUT
intr_rx_watermark_o	Yes	Yes	T216,T314,T217	Yes	T216,T314,T217	OUTPUT
intr_tx_done_o	Yes	Yes	T216,T314,T217	Yes	T216,T314,T217	OUTPUT
intr_rx_overflow_o	Yes	Yes	T216,T314,T217	Yes	T216,T314,T217	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_break_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_timeout_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T153,T154,T314	Yes	T153,T154,T314	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T153,T154,T314	Yes	T153,T154,T314	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T78	Yes	T67,T68,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T79,T51,T80	Yes	T79,T51,T80	INPUT
tl_i.a_valid	Yes	Yes	T164,T250,T153	Yes	T164,T250,T153	INPUT
tl_o.a_ready	Yes	Yes	T164,T250,T153	Yes	T164,T250,T153	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T81	Yes	T75,T76,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T153,T154,T314	Yes	T153,T154,T314	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T164,T250,T153	Yes	T164,T250,T153	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T164,T250,T153	Yes	T164,T250,T153	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T224,*T150,*T75	Yes	T224,T150,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T153,*T154,*T314	Yes	T153,T154,T314	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T164,T250,T153	Yes	T164,T250,T153	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T164,T83,T250	Yes	T164,T83,T250	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T164,T83,T250	Yes	T164,T83,T250	OUTPUT
cio_rx_i	Yes	Yes	T153,T154,T333	Yes	T153,T154,T333	INPUT
cio_tx_o	Yes	Yes	T153,T154,T333	Yes	T153,T154,T333	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T153,T154,T314	Yes	T153,T154,T314	OUTPUT
intr_tx_empty_o	Yes	Yes	T153,T154,T314	Yes	T153,T154,T314	OUTPUT
intr_rx_watermark_o	Yes	Yes	T153,T154,T314	Yes	T153,T154,T314	OUTPUT
intr_tx_done_o	Yes	Yes	T153,T154,T314	Yes	T153,T154,T314	OUTPUT
intr_rx_overflow_o	Yes	Yes	T153,T154,T314	Yes	T153,T154,T314	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_break_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_timeout_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T15,T16,T314	Yes	T15,T16,T314	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T15,T16,T314	Yes	T15,T16,T314	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T78	Yes	T67,T68,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T79,T51,T80	Yes	T79,T51,T80	INPUT
tl_i.a_valid	Yes	Yes	T15,T164,T250	Yes	T15,T164,T250	INPUT
tl_o.a_ready	Yes	Yes	T15,T164,T250	Yes	T15,T164,T250	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T15,T16,T314	Yes	T15,T16,T314	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T15,T164,T250	Yes	T15,T164,T250	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T15,T164,T250	Yes	T15,T164,T250	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T224,*T150,*T75	Yes	T224,T150,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T15,*T16,*T314	Yes	T15,T16,T314	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T15,T164,T250	Yes	T15,T164,T250	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T164,T83,T250	Yes	T164,T83,T250	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T164,T83,T250	Yes	T164,T83,T250	OUTPUT
cio_rx_i	Yes	Yes	T15,T16,T349	Yes	T15,T16,T349	INPUT
cio_tx_o	Yes	Yes	T15,T16,T349	Yes	T15,T16,T349	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T15,T16,T314	Yes	T15,T16,T314	OUTPUT
intr_tx_empty_o	Yes	Yes	T15,T16,T314	Yes	T15,T16,T314	OUTPUT
intr_rx_watermark_o	Yes	Yes	T15,T16,T314	Yes	T15,T16,T314	OUTPUT
intr_tx_done_o	Yes	Yes	T15,T16,T314	Yes	T15,T16,T314	OUTPUT
intr_rx_overflow_o	Yes	Yes	T15,T16,T314	Yes	T15,T16,T314	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_break_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_timeout_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T314,T321,T322	Yes	T314,T321,T322	OUTPUT

*Tests covering at least one bit in the range