Line Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 57 | 0 | 0 | |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 57 |
|
unreachable |
| 64 |
1 |
1 |
| 66 |
1 |
1 |
| 71 |
1 |
1 |
Line Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Line Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 2 | 66.67 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 102 | 0 | 0 | |
| CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
0 |
1 |
| 102 |
|
unreachable |
| 114 |
1 |
1 |
| 115 |
1 |
1 |
Cond Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T30,T31,T32 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 64
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T30,T31,T32 |
| 1 | Covered | T1,T2,T3 |
LINE 66
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T30,T31,T32 |
| 1 | 1 | Covered | T30,T31,T32 |
LINE 71
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T30,T31,T32 |
Cond Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 4 | 2 | 50.00 |
| Logical | 4 | 2 | 50.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T30,T31,T32 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T30,T31,T32 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T30,T31,T32 |
| 1 | 1 | Covered | T30,T31,T32 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T30,T31,T32 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T30,T31,T32 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T12,T13,T9 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T38,T39,T40 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T9,T20,T24 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T34 |
| 1 | 0 | Covered | T12,T13,T9 |
| 1 | 1 | Covered | T9,T20,T24 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T13,T9 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T9,T20,T24 |
| 1 | 1 | Covered | T12,T13,T9 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T12,T13 |
Branch Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| TERNARY |
71 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T30,T31,T32 |
LineNo. Expression
-1-: 71 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T30,T31,T32 |
| 0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T30,T31,T32 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T9,T20,T24 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T13,T9 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T12,T13 |
| 0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
1 |
50.00 |
| TERNARY |
114 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 114 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Not Covered |
|
Assert Coverage for Module :
prim_generic_pad_wrapper
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
71470 |
71470 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
71470 |
71470 |
0 |
0 |
| T1 |
70 |
70 |
0 |
0 |
| T2 |
70 |
70 |
0 |
0 |
| T3 |
70 |
70 |
0 |
0 |
| T4 |
70 |
70 |
0 |
0 |
| T5 |
70 |
70 |
0 |
0 |
| T34 |
70 |
70 |
0 |
0 |
| T59 |
70 |
70 |
0 |
0 |
| T86 |
70 |
70 |
0 |
0 |
| T87 |
70 |
70 |
0 |
0 |
| T88 |
70 |
70 |
0 |
0 |
