Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T188,T51,T304
0	1	Covered	T188,T304,T305
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T304,T305
1	Covered	T188,T51,T304

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T304,T305
1	Covered	T188,T51,T304

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T188,T304,T305
1	1	Covered	T188,T304,T305

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T188,T51,T304
1	0	Covered	T188,T304,T305
1	1	Covered	T188,T304,T305

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T188,T304,T305

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T51,T304
0	Covered	T188,T304,T305

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T51,T304
0	Covered	T188,T304,T305

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1046710868	1030365240	0	0
CheckNGreaterZero_A	2042	2042	0	0
GntImpliesReady_A	1046710868	8384	0	0
GntImpliesValid_A	1046710868	8384	0	0
GrantKnown_A	1046710868	1030365240	0	0
IdxKnown_A	1046710868	1030365240	0	0
IndexIsCorrect_A	1046710868	8384	0	0
NoReadyValidNoGrant_A	1046710868	0	0	0
Priority_A	1046710868	8384	0	0
ReadyAndValidImplyGrant_A	1046710868	8384	0	0
ReqAndReadyImplyGrant_A	1046710868	8384	0	0
ReqImpliesValid_A	1046710868	8384	0	0
ValidKnown_A	1046710868	1030365240	0	0
gen_data_port_assertion.DataFlow_A	1046710868	8384	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	1030365240	0	0
T1	472232	472006	0	0
T2	494824	494592	0	0
T3	256284	256274	0	0
T4	306000	305884	0	0
T5	287876	287752	0	0
T34	202890	202766	0	0
T59	325044	324934	0	0
T86	113066	112956	0	0
T87	139144	139034	0	0
T88	148474	148372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T34	2	2	0	0
T59	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0
T88	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	8384	0	0
T135	351516	0	0	0
T188	201184	2795	0	0
T236	1689728	0	0	0
T252	560390	0	0	0
T304	0	2794	0	0
T305	0	2795	0	0
T394	252852	0	0	0
T395	270284	0	0	0
T396	181018	0	0	0
T397	1036052	0	0	0
T398	194556	0	0	0
T399	1151916	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	8384	0	0
T135	351516	0	0	0
T188	201184	2795	0	0
T236	1689728	0	0	0
T252	560390	0	0	0
T304	0	2794	0	0
T305	0	2795	0	0
T394	252852	0	0	0
T395	270284	0	0	0
T396	181018	0	0	0
T397	1036052	0	0	0
T398	194556	0	0	0
T399	1151916	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	1030365240	0	0
T1	472232	472006	0	0
T2	494824	494592	0	0
T3	256284	256274	0	0
T4	306000	305884	0	0
T5	287876	287752	0	0
T34	202890	202766	0	0
T59	325044	324934	0	0
T86	113066	112956	0	0
T87	139144	139034	0	0
T88	148474	148372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	1030365240	0	0
T1	472232	472006	0	0
T2	494824	494592	0	0
T3	256284	256274	0	0
T4	306000	305884	0	0
T5	287876	287752	0	0
T34	202890	202766	0	0
T59	325044	324934	0	0
T86	113066	112956	0	0
T87	139144	139034	0	0
T88	148474	148372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	8384	0	0
T135	351516	0	0	0
T188	201184	2795	0	0
T236	1689728	0	0	0
T252	560390	0	0	0
T304	0	2794	0	0
T305	0	2795	0	0
T394	252852	0	0	0
T395	270284	0	0	0
T396	181018	0	0	0
T397	1036052	0	0	0
T398	194556	0	0	0
T399	1151916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	8384	0	0
T135	351516	0	0	0
T188	201184	2795	0	0
T236	1689728	0	0	0
T252	560390	0	0	0
T304	0	2794	0	0
T305	0	2795	0	0
T394	252852	0	0	0
T395	270284	0	0	0
T396	181018	0	0	0
T397	1036052	0	0	0
T398	194556	0	0	0
T399	1151916	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	8384	0	0
T135	351516	0	0	0
T188	201184	2795	0	0
T236	1689728	0	0	0
T252	560390	0	0	0
T304	0	2794	0	0
T305	0	2795	0	0
T394	252852	0	0	0
T395	270284	0	0	0
T396	181018	0	0	0
T397	1036052	0	0	0
T398	194556	0	0	0
T399	1151916	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	8384	0	0
T135	351516	0	0	0
T188	201184	2795	0	0
T236	1689728	0	0	0
T252	560390	0	0	0
T304	0	2794	0	0
T305	0	2795	0	0
T394	252852	0	0	0
T395	270284	0	0	0
T396	181018	0	0	0
T397	1036052	0	0	0
T398	194556	0	0	0
T399	1151916	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	8384	0	0
T135	351516	0	0	0
T188	201184	2795	0	0
T236	1689728	0	0	0
T252	560390	0	0	0
T304	0	2794	0	0
T305	0	2795	0	0
T394	252852	0	0	0
T395	270284	0	0	0
T396	181018	0	0	0
T397	1036052	0	0	0
T398	194556	0	0	0
T399	1151916	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	1030365240	0	0
T1	472232	472006	0	0
T2	494824	494592	0	0
T3	256284	256274	0	0
T4	306000	305884	0	0
T5	287876	287752	0	0
T34	202890	202766	0	0
T59	325044	324934	0	0
T86	113066	112956	0	0
T87	139144	139034	0	0
T88	148474	148372	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046710868	8384	0	0
T135	351516	0	0	0
T188	201184	2795	0	0
T236	1689728	0	0	0
T252	560390	0	0	0
T304	0	2794	0	0
T305	0	2795	0	0
T394	252852	0	0	0
T395	270284	0	0	0
T396	181018	0	0	0
T397	1036052	0	0	0
T398	194556	0	0	0
T399	1151916	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T188,T51,T304
0	1	Covered	T188,T304,T305
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T304,T305
1	Covered	T188,T51,T304

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T304,T305
1	Covered	T188,T51,T304

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T188,T304,T305
1	1	Covered	T188,T304,T305

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T188,T51,T304
1	0	Covered	T188,T304,T305
1	1	Covered	T188,T304,T305

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T188,T304,T305

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T51,T304
0	Covered	T188,T304,T305

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T51,T304
0	Covered	T188,T304,T305

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	523355434	515182620	0	0
CheckNGreaterZero_A	1021	1021	0	0
GntImpliesReady_A	523355434	5196	0	0
GntImpliesValid_A	523355434	5196	0	0
GrantKnown_A	523355434	515182620	0	0
IdxKnown_A	523355434	515182620	0	0
IndexIsCorrect_A	523355434	5196	0	0
NoReadyValidNoGrant_A	523355434	0	0	0
Priority_A	523355434	5196	0	0
ReadyAndValidImplyGrant_A	523355434	5196	0	0
ReqAndReadyImplyGrant_A	523355434	5196	0	0
ReqImpliesValid_A	523355434	5196	0	0
ValidKnown_A	523355434	515182620	0	0
gen_data_port_assertion.DataFlow_A	523355434	5196	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	515182620	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	5196	0	0
T135	175758	0	0	0
T188	100592	1733	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1731	0	0
T305	0	1732	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	5196	0	0
T135	175758	0	0	0
T188	100592	1733	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1731	0	0
T305	0	1732	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	515182620	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	515182620	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	5196	0	0
T135	175758	0	0	0
T188	100592	1733	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1731	0	0
T305	0	1732	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	5196	0	0
T135	175758	0	0	0
T188	100592	1733	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1731	0	0
T305	0	1732	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	5196	0	0
T135	175758	0	0	0
T188	100592	1733	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1731	0	0
T305	0	1732	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	5196	0	0
T135	175758	0	0	0
T188	100592	1733	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1731	0	0
T305	0	1732	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	5196	0	0
T135	175758	0	0	0
T188	100592	1733	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1731	0	0
T305	0	1732	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	515182620	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	5196	0	0
T135	175758	0	0	0
T188	100592	1733	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1731	0	0
T305	0	1732	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T188,T51,T304
0	1	Covered	T188,T304,T305
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T304,T305
1	Covered	T188,T51,T304

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T304,T305
1	Covered	T188,T51,T304

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T188,T304,T305
1	1	Covered	T188,T304,T305

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T188,T51,T304
1	0	Covered	T188,T304,T305
1	1	Covered	T188,T304,T305

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T188,T304,T305

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T51,T304
0	Covered	T188,T304,T305

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T51,T304
0	Covered	T188,T304,T305

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	523355434	515182620	0	0
CheckNGreaterZero_A	1021	1021	0	0
GntImpliesReady_A	523355434	3188	0	0
GntImpliesValid_A	523355434	3188	0	0
GrantKnown_A	523355434	515182620	0	0
IdxKnown_A	523355434	515182620	0	0
IndexIsCorrect_A	523355434	3188	0	0
NoReadyValidNoGrant_A	523355434	0	0	0
Priority_A	523355434	3188	0	0
ReadyAndValidImplyGrant_A	523355434	3188	0	0
ReqAndReadyImplyGrant_A	523355434	3188	0	0
ReqImpliesValid_A	523355434	3188	0	0
ValidKnown_A	523355434	515182620	0	0
gen_data_port_assertion.DataFlow_A	523355434	3188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	515182620	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	3188	0	0
T135	175758	0	0	0
T188	100592	1062	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1063	0	0
T305	0	1063	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	3188	0	0
T135	175758	0	0	0
T188	100592	1062	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1063	0	0
T305	0	1063	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	515182620	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	515182620	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	3188	0	0
T135	175758	0	0	0
T188	100592	1062	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1063	0	0
T305	0	1063	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	3188	0	0
T135	175758	0	0	0
T188	100592	1062	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1063	0	0
T305	0	1063	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	3188	0	0
T135	175758	0	0	0
T188	100592	1062	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1063	0	0
T305	0	1063	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	3188	0	0
T135	175758	0	0	0
T188	100592	1062	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1063	0	0
T305	0	1063	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	3188	0	0
T135	175758	0	0	0
T188	100592	1062	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1063	0	0
T305	0	1063	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	515182620	0	0
T1	236116	236003	0	0
T2	247412	247296	0	0
T3	128142	128137	0	0
T4	153000	152942	0	0
T5	143938	143876	0	0
T34	101445	101383	0	0
T59	162522	162467	0	0
T86	56533	56478	0	0
T87	69572	69517	0	0
T88	74237	74186	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523355434	3188	0	0
T135	175758	0	0	0
T188	100592	1062	0	0
T236	844864	0	0	0
T252	280195	0	0	0
T304	0	1063	0	0
T305	0	1063	0	0
T394	126426	0	0	0
T395	135142	0	0	0
T396	90509	0	0	0
T397	518026	0	0	0
T398	97278	0	0	0
T399	575958	0	0	0