Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3763402	1			T72	1010		T73	143		T74	436
values[2]	746207	1			T72	313		T73	51		T74	71
values[3]	105880	1			T72	18		T74	19		T258	155
values[4]	56754	1			T72	1		T74	1		T258	3
values[5]	37388	1			T74	4		T441	19		T549	1
values[6]	27150	1			T74	1		T441	19		T693	2
values[7]	21394	1			T74	3		T441	20		T693	2
values[8]	18446	1			T74	5		T441	19		T693	2
values[9]	16465	1			T74	4		T441	19		T693	2
values[10]	14935	1			T74	6		T441	19		T693	2
values[11]	13714	1			T74	18		T441	20		T693	2
values[12]	12953	1			T74	34		T441	19		T693	2
values[13]	12350	1			T74	38		T441	19		T693	2
values[14]	11897	1			T74	18		T441	19		T693	2
values[15]	11184	1			T74	19		T441	19		T693	2
values[16]	10563	1			T74	13		T441	19		T693	2
values[17]	10258	1			T74	3		T441	19		T693	2
values[18]	9654	1			T441	20		T693	2		T447	9
values[19]	9615	1			T441	19		T693	2		T447	9
values[20]	9366	1			T441	19		T693	2		T447	9
values[21]	9049	1			T441	19		T693	2		T447	9
values[22]	8592	1			T441	19		T693	2		T447	9
values[23]	8465	1			T441	19		T693	2		T447	10
values[24]	8381	1			T441	19		T693	2		T447	9
values[25]	7896	1			T441	20		T693	2		T447	9
values[26]	7950	1			T441	19		T693	2		T447	9
values[27]	7487	1			T441	19		T693	2		T447	9
values[28]	7173	1			T441	19		T693	2		T447	9
values[29]	6682	1			T441	19		T693	2		T447	9
values[30]	6197	1			T441	19		T693	2		T447	9
values[31]	5731	1			T441	19		T693	2		T447	9
values[32]	5340	1			T441	19		T693	2		T447	10
values[33]	4792	1			T441	19		T693	2		T447	9
values[34]	4523	1			T441	19		T693	2		T447	9
values[35]	4169	1			T441	19		T693	2		T447	9
values[36]	3899	1			T441	19		T693	2		T447	9
values[37]	3645	1			T441	19		T693	2		T447	9
values[38]	3635	1			T441	19		T693	2		T447	9
values[39]	3465	1			T441	19		T693	2		T447	9
values[40]	3316	1			T441	19		T693	2		T447	9
values[41]	3332	1			T441	20		T693	3		T447	10
values[42]	3188	1			T441	19		T693	2		T447	9
values[43]	3095	1			T441	19		T693	2		T447	9
values[44]	3118	1			T441	20		T693	2		T447	10
values[45]	3015	1			T441	21		T693	2		T447	9
values[46]	2965	1			T441	19		T693	2		T447	9
values[47]	2778	1			T441	20		T693	2		T447	9
values[48]	2765	1			T441	19		T693	2		T447	9
values[49]	2750	1			T441	19		T693	2		T447	9
values[50]	2676	1			T441	19		T693	2		T447	9
values[51]	2742	1			T441	19		T693	2		T447	9
values[52]	2644	1			T441	21		T693	2		T447	9
values[53]	2576	1			T441	19		T693	2		T447	9
values[54]	2527	1			T441	19		T693	2		T447	9
values[55]	2476	1			T441	20		T693	2		T447	9
values[56]	2412	1			T441	19		T693	2		T447	9
values[57]	2439	1			T441	20		T693	2		T447	9
values[58]	2434	1			T441	19		T693	2		T447	9
values[59]	2434	1			T441	19		T693	2		T447	9
values[60]	2462	1			T441	20		T693	2		T447	9
values[61]	2638	1			T441	19		T693	2		T447	9
values[62]	4125	1			T441	20		T693	2		T447	9
values[63]	11350	1			T441	20		T693	2		T447	10
values[64]	212311	1			T441	3503		T693	359		T447	1692

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4766766	1			T72	1029		T73	81		T74	1399
values[2]	804397	1			T72	302		T73	22		T74	215
values[3]	84499	1			T72	89		T74	18		T257	2
values[4]	14655	1			T72	26		T74	1		T258	34
values[5]	5493	1			T72	7		T258	14		T441	25
values[6]	3211	1			T72	4		T258	5		T441	6
values[7]	2537	1			T72	2		T258	1		T441	3
values[8]	2143	1			T441	1		T447	1		T552	12
values[9]	1946	1			T441	1		T552	9		T553	33
values[10]	1575	1			T441	1		T552	7		T553	17
values[11]	1362	1			T441	1		T553	26		T472	3
values[12]	1283	1			T441	1		T553	19		T485	1
values[13]	1191	1			T441	1		T553	11		T485	1
values[14]	1185	1			T441	1		T553	6		T485	1
values[15]	1181	1			T441	1		T553	5		T485	1
values[16]	1182	1			T441	1		T553	6		T485	1
values[17]	1134	1			T441	1		T553	6		T485	1
values[18]	1069	1			T441	1		T553	6		T485	1
values[19]	1001	1			T441	1		T553	5		T485	1
values[20]	935	1			T441	1		T553	2		T485	1
values[21]	916	1			T441	1		T553	1		T485	1
values[22]	805	1			T441	1		T553	1		T485	1
values[23]	854	1			T441	1		T553	1		T485	1
values[24]	777	1			T441	1		T553	1		T485	1
values[25]	715	1			T441	1		T553	1		T485	1
values[26]	637	1			T441	1		T553	1		T485	1
values[27]	665	1			T441	1		T553	2		T485	1
values[28]	650	1			T441	1		T553	5		T485	1
values[29]	666	1			T441	1		T553	6		T485	1
values[30]	600	1			T441	1		T553	8		T485	1
values[31]	601	1			T441	1		T553	5		T485	1
values[32]	551	1			T441	1		T553	3		T485	1
values[33]	540	1			T441	1		T553	2		T485	1
values[34]	499	1			T441	1		T553	1		T485	1
values[35]	505	1			T441	1		T553	4		T485	1
values[36]	567	1			T441	1		T553	3		T485	1
values[37]	545	1			T441	1		T553	1		T485	2
values[38]	490	1			T441	1		T553	7		T485	1
values[39]	508	1			T441	1		T553	3		T485	1
values[40]	511	1			T441	1		T553	6		T485	1
values[41]	482	1			T441	1		T553	6		T485	1
values[42]	430	1			T441	1		T553	10		T485	1
values[43]	437	1			T441	1		T553	10		T485	1
values[44]	402	1			T441	1		T553	6		T485	1
values[45]	407	1			T441	1		T553	3		T485	1
values[46]	399	1			T441	1		T553	1		T485	1
values[47]	395	1			T441	1		T553	7		T485	1
values[48]	400	1			T441	1		T553	2		T485	1
values[49]	402	1			T441	1		T553	6		T485	1
values[50]	408	1			T441	1		T553	6		T485	1
values[51]	402	1			T441	1		T553	8		T485	1
values[52]	376	1			T441	1		T553	4		T485	1
values[53]	342	1			T441	1		T553	3		T485	1
values[54]	373	1			T441	2		T553	1		T485	1
values[55]	384	1			T441	1		T485	1		T539	9
values[56]	375	1			T441	1		T485	1		T539	7
values[57]	337	1			T441	1		T485	1		T539	3
values[58]	371	1			T441	1		T485	1		T539	2
values[59]	356	1			T441	1		T485	1		T539	3
values[60]	356	1			T441	1		T485	1		T539	6
values[61]	386	1			T441	1		T485	1		T539	4
values[62]	621	1			T441	1		T485	1		T539	11
values[63]	2128	1			T441	1		T485	1		T539	41
values[64]	22720	1			T441	191		T485	137		T539	66

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	579784	1			T72	10		T73	1		T74	99
values[2]	2647916	1			T72	1066		T73	109		T74	237
values[3]	1209334	1			T72	392		T73	27		T74	242
values[4]	147750	1			T72	23		T74	37		T257	4
values[5]	76338	1			T72	4		T74	27		T258	20
values[6]	49785	1			T74	2		T258	1		T441	19
values[7]	35983	1			T441	19		T693	2		T447	9
values[8]	27708	1			T441	19		T693	2		T447	9
values[9]	23089	1			T441	19		T693	2		T447	9
values[10]	20128	1			T441	19		T693	2		T447	9
values[11]	18542	1			T441	19		T693	2		T447	9
values[12]	16714	1			T441	20		T693	2		T447	9
values[13]	15334	1			T441	19		T693	2		T447	9
values[14]	14756	1			T441	19		T693	2		T447	9
values[15]	14387	1			T441	19		T693	2		T447	9
values[16]	13616	1			T441	19		T693	2		T447	9
values[17]	12633	1			T441	19		T693	2		T447	9
values[18]	11906	1			T441	19		T693	2		T447	9
values[19]	11713	1			T441	19		T693	2		T447	9
values[20]	11458	1			T441	19		T693	2		T447	10
values[21]	11078	1			T441	20		T693	2		T447	9
values[22]	10289	1			T441	19		T693	2		T447	9
values[23]	9768	1			T441	19		T693	2		T447	9
values[24]	9538	1			T441	19		T693	2		T447	10
values[25]	9003	1			T441	19		T693	2		T447	9
values[26]	8654	1			T441	19		T693	2		T447	9
values[27]	8520	1			T441	19		T693	2		T447	9
values[28]	7880	1			T441	19		T693	2		T447	9
values[29]	7316	1			T441	19		T693	2		T447	9
values[30]	6614	1			T441	19		T693	2		T447	9
values[31]	6123	1			T441	20		T693	2		T447	9
values[32]	5666	1			T441	19		T693	2		T447	9
values[33]	5467	1			T441	19		T693	2		T447	9
values[34]	5154	1			T441	19		T693	2		T447	10
values[35]	4827	1			T441	19		T693	2		T447	9
values[36]	4612	1			T441	20		T693	2		T447	9
values[37]	4236	1			T441	19		T693	2		T447	9
values[38]	3958	1			T441	20		T693	2		T447	10
values[39]	3777	1			T441	19		T693	2		T447	10
values[40]	3714	1			T441	19		T693	2		T447	9
values[41]	3695	1			T441	19		T693	2		T447	9
values[42]	3510	1			T441	19		T693	2		T447	9
values[43]	3455	1			T441	19		T693	2		T447	9
values[44]	3321	1			T441	19		T693	2		T447	9
values[45]	3229	1			T441	19		T693	2		T447	9
values[46]	3157	1			T441	21		T693	2		T447	9
values[47]	3144	1			T441	19		T693	2		T447	9
values[48]	3138	1			T441	19		T693	2		T447	9
values[49]	3104	1			T441	19		T693	2		T447	9
values[50]	3080	1			T441	19		T693	2		T447	9
values[51]	3030	1			T441	19		T693	2		T447	9
values[52]	3029	1			T441	19		T693	2		T447	9
values[53]	2991	1			T441	19		T693	2		T447	9
values[54]	2934	1			T441	19		T693	3		T447	10
values[55]	2913	1			T441	20		T693	2		T447	9
values[56]	2869	1			T441	19		T693	2		T447	10
values[57]	2717	1			T441	19		T693	2		T447	9
values[58]	2675	1			T441	19		T693	2		T447	9
values[59]	2652	1			T441	19		T693	2		T447	9
values[60]	2618	1			T441	19		T693	2		T447	9
values[61]	2730	1			T441	19		T693	2		T447	9
values[62]	3632	1			T441	19		T693	2		T447	9
values[63]	9201	1			T441	22		T693	3		T447	10
values[64]	202481	1			T441	3650		T693	356		T447	1644