Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2414704	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37843390

1

T1

5775

T2

4804

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28472267	1			T1	2491		T2	1538		T4	31366
values[0x0]	10242558	1			T1	3284		T2	3266		T3	23
values[0x1]	1543269	1			T1	444		T2	133		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	942255	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39315839

1

T1

6219

T2

4937

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18514846	1			T1	3110		T2	2469		T4	17256
valid_sources[0x01]	18511776	1			T1	3109		T2	2468		T4	17255
valid_sources[0x02]	52284	1			T164	8		T142	6459		T143	840
valid_sources[0x03]	51321	1			T76	1		T142	6366		T143	793
valid_sources[0x04]	51410	1			T76	1		T142	6266		T143	814
valid_sources[0x05]	51408	1			T142	6350		T143	777		T144	121
valid_sources[0x06]	53026	1			T47	1		T178	41		T142	6458
valid_sources[0x07]	52178	1			T47	1		T142	6459		T143	821
valid_sources[0x08]	52031	1			T3	10		T142	6380		T143	780
valid_sources[0x09]	51542	1			T76	1		T142	6391		T143	841
valid_sources[0x0a]	52180	1			T68	39		T76	1		T47	3
valid_sources[0x0b]	52054	1			T47	2		T163	39		T142	6341
valid_sources[0x0c]	51653	1			T76	1		T47	1		T142	6424
valid_sources[0x0d]	52230	1			T76	1		T142	6431		T143	759
valid_sources[0x0e]	51379	1			T142	6290		T143	781		T144	70
valid_sources[0x0f]	52180	1			T76	2		T142	6352		T143	787
valid_sources[0x10]	52467	1			T76	1		T164	2		T178	20
valid_sources[0x11]	51057	1			T142	6151		T143	813		T144	46
valid_sources[0x12]	52223	1			T76	2		T47	4		T142	6424
valid_sources[0x13]	52661	1			T76	2		T47	2		T178	430
valid_sources[0x14]	52266	1			T76	1		T142	6401		T143	806
valid_sources[0x15]	51795	1			T142	6169		T143	840		T144	44
valid_sources[0x16]	51367	1			T178	2		T142	6387		T143	787
valid_sources[0x17]	52258	1			T178	5		T142	6231		T143	786
valid_sources[0x18]	51555	1			T76	1		T47	2		T142	6311
valid_sources[0x19]	52048	1			T76	1		T142	6397		T143	751
valid_sources[0x1a]	52527	1			T47	1		T178	2		T142	6431
valid_sources[0x1b]	52525	1			T3	1		T76	1		T47	2
valid_sources[0x1c]	51671	1			T47	2		T142	6312		T143	799
valid_sources[0x1d]	52341	1			T76	1		T178	9		T142	6236
valid_sources[0x1e]	51480	1			T164	8		T178	2		T142	6493
valid_sources[0x1f]	55110	1			T47	1		T178	15		T142	6361
valid_sources[0x20]	52909	1			T47	1		T142	6478		T143	796

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27371349

1

T1

2491

T2

1538

T4

31366

values[0x0]

all_enables

biggest_size

10180789

1

T1

3284

T2

3266

T3

23

values[0x1]

all_enables

biggest_size

291252

1

T3

16

T68

19

T76

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2935409	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

463391

1

T72

179

T73

32

T74

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1150921	1			T72	404		T73	60		T74	14
values[0x0]	1098699	1			T72	484		T73	66		T74	4
values[0x1]	1149180	1			T72	454		T73	68		T74	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2273536	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1125264

1

T72

444

T73

72

T74

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52899	1			T72	26		T73	2		T214	21
valid_sources[0x01]	53056	1			T72	37		T73	3		T74	1
valid_sources[0x02]	53481	1			T72	23		T73	3		T74	2
valid_sources[0x03]	52820	1			T72	35		T73	3		T74	1
valid_sources[0x04]	54056	1			T72	26		T73	4		T74	2
valid_sources[0x05]	52984	1			T72	19		T73	4		T74	2
valid_sources[0x06]	52118	1			T72	16		T73	2		T74	1
valid_sources[0x07]	52191	1			T72	21		T73	5		T214	29
valid_sources[0x08]	54318	1			T72	15		T73	1		T214	32
valid_sources[0x09]	54022	1			T72	22		T73	3		T74	2
valid_sources[0x0a]	51721	1			T72	17		T73	1		T74	1
valid_sources[0x0b]	53175	1			T72	13		T73	1		T74	1
valid_sources[0x0c]	53498	1			T72	30		T73	2		T74	2
valid_sources[0x0d]	53941	1			T72	22		T73	3		T214	60
valid_sources[0x0e]	53781	1			T72	37		T73	1		T214	33
valid_sources[0x0f]	52448	1			T72	19		T73	4		T214	42
valid_sources[0x10]	52469	1			T72	15		T73	3		T214	38
valid_sources[0x11]	52602	1			T72	24		T73	5		T214	20
valid_sources[0x12]	52837	1			T72	33		T73	3		T214	32
valid_sources[0x13]	52585	1			T72	15		T73	5		T214	12
valid_sources[0x14]	55186	1			T72	5		T73	3		T74	1
valid_sources[0x15]	53090	1			T72	20		T73	4		T214	15
valid_sources[0x16]	53186	1			T72	23		T73	4		T74	1
valid_sources[0x17]	52811	1			T72	24		T73	3		T214	44
valid_sources[0x18]	52601	1			T72	16		T73	3		T74	1
valid_sources[0x19]	53396	1			T72	16		T73	5		T214	42
valid_sources[0x1a]	53220	1			T72	18		T73	2		T74	1
valid_sources[0x1b]	53675	1			T72	22		T73	4		T214	17
valid_sources[0x1c]	52974	1			T72	17		T73	1		T74	1
valid_sources[0x1d]	52099	1			T72	22		T73	1		T214	21
valid_sources[0x1e]	53394	1			T72	38		T73	3		T214	63
valid_sources[0x1f]	52876	1			T72	14		T73	5		T214	14
valid_sources[0x20]	51436	1			T72	32		T73	1		T214	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48504

1

T72

12

T73

3

T74

3

values[0x0]

all_enables

biggest_size

366347

1

T72

150

T73

27

T74

1

values[0x1]

all_enables

biggest_size

48540

1

T72

17

T73

2

T214

32

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3124804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

508770

1

T72

192

T73

16

T74

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1242883	1			T72	487		T73	28		T74	28
values[0x0]	1146691	1			T72	478		T73	41		T74	3
values[0x1]	1244000	1			T72	494		T73	34		T74	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2397650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1235924

1

T72

488

T73

30

T74

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56845	1			T72	21		T73	2		T74	1
valid_sources[0x01]	57141	1			T72	9		T73	1		T74	1
valid_sources[0x02]	56669	1			T72	23		T73	3		T214	48
valid_sources[0x03]	56693	1			T72	25		T73	1		T74	1
valid_sources[0x04]	56816	1			T72	26		T73	1		T214	24
valid_sources[0x05]	55708	1			T72	11		T73	3		T214	55
valid_sources[0x06]	57408	1			T72	20		T214	27		T258	11
valid_sources[0x07]	55795	1			T72	28		T73	2		T74	1
valid_sources[0x08]	56868	1			T72	35		T73	1		T214	58
valid_sources[0x09]	57467	1			T72	15		T73	7		T74	2
valid_sources[0x0a]	55841	1			T72	23		T214	59		T258	25
valid_sources[0x0b]	56767	1			T72	9		T214	27		T258	18
valid_sources[0x0c]	58137	1			T72	30		T74	1		T214	35
valid_sources[0x0d]	57281	1			T72	32		T74	1		T214	60
valid_sources[0x0e]	56759	1			T72	17		T214	19		T257	1
valid_sources[0x0f]	56305	1			T72	30		T74	1		T214	47
valid_sources[0x10]	56558	1			T72	41		T214	57		T258	46
valid_sources[0x11]	56638	1			T72	32		T214	29		T257	1
valid_sources[0x12]	56709	1			T72	26		T214	21		T257	1
valid_sources[0x13]	56501	1			T72	26		T73	2		T214	39
valid_sources[0x14]	57636	1			T72	29		T73	6		T74	1
valid_sources[0x15]	56338	1			T72	28		T214	6		T257	1
valid_sources[0x16]	56521	1			T72	29		T73	1		T74	1
valid_sources[0x17]	57514	1			T72	18		T74	2		T214	44
valid_sources[0x18]	56225	1			T72	24		T73	3		T74	4
valid_sources[0x19]	57370	1			T72	23		T73	2		T74	2
valid_sources[0x1a]	56417	1			T72	50		T73	3		T214	38
valid_sources[0x1b]	57234	1			T72	24		T73	2		T74	1
valid_sources[0x1c]	57032	1			T72	19		T74	2		T214	16
valid_sources[0x1d]	56979	1			T72	18		T74	2		T214	21
valid_sources[0x1e]	56967	1			T72	11		T74	1		T214	47
valid_sources[0x1f]	57681	1			T72	19		T73	1		T214	15
valid_sources[0x20]	56242	1			T72	35		T74	1		T214	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53468

1

T72

20

T73

1

T74

1

values[0x0]

all_enables

biggest_size

402000

1

T72

154

T73

13

T214

249

values[0x1]

all_enables

biggest_size

53302

1

T72

18

T73

2

T74

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2954239	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

467573

1

T72

206

T73

20

T74

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1158306	1			T72	476		T73	43		T74	10
values[0x0]	1104991	1			T72	489		T73	48		T74	2
values[0x1]	1158515	1			T72	530		T73	46		T74	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2288870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1132942

1

T72

493

T73

49

T74

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52942	1			T72	24		T73	1		T214	14
valid_sources[0x01]	53714	1			T72	19		T73	2		T214	41
valid_sources[0x02]	53605	1			T72	24		T73	3		T74	1
valid_sources[0x03]	53626	1			T72	23		T73	3		T214	39
valid_sources[0x04]	52759	1			T72	22		T73	3		T74	1
valid_sources[0x05]	52920	1			T72	21		T73	4		T214	33
valid_sources[0x06]	52968	1			T72	21		T73	1		T214	33
valid_sources[0x07]	53318	1			T72	24		T73	5		T214	28
valid_sources[0x08]	54051	1			T72	24		T73	1		T74	1
valid_sources[0x09]	53923	1			T72	26		T73	4		T214	46
valid_sources[0x0a]	52785	1			T72	22		T73	4		T214	79
valid_sources[0x0b]	53591	1			T72	25		T73	2		T214	25
valid_sources[0x0c]	53779	1			T72	22		T73	1		T74	2
valid_sources[0x0d]	53164	1			T72	32		T73	3		T214	69
valid_sources[0x0e]	53802	1			T72	23		T73	3		T214	34
valid_sources[0x0f]	53378	1			T72	21		T73	3		T214	34
valid_sources[0x10]	52828	1			T72	15		T73	4		T214	56
valid_sources[0x11]	52710	1			T72	17		T73	2		T74	1
valid_sources[0x12]	53567	1			T72	22		T73	6		T214	35
valid_sources[0x13]	54852	1			T72	20		T73	2		T74	1
valid_sources[0x14]	53696	1			T72	17		T73	2		T214	50
valid_sources[0x15]	53523	1			T72	30		T73	2		T74	1
valid_sources[0x16]	52757	1			T72	20		T73	2		T214	46
valid_sources[0x17]	52448	1			T72	25		T73	1		T214	38
valid_sources[0x18]	53387	1			T72	29		T73	3		T214	17
valid_sources[0x19]	52978	1			T72	24		T73	2		T214	32
valid_sources[0x1a]	53910	1			T72	23		T73	1		T214	35
valid_sources[0x1b]	53471	1			T72	15		T214	26		T257	1
valid_sources[0x1c]	52853	1			T72	28		T214	6		T257	1
valid_sources[0x1d]	53744	1			T72	23		T73	4		T214	27
valid_sources[0x1e]	53568	1			T72	19		T73	5		T214	45
valid_sources[0x1f]	53154	1			T72	26		T73	3		T214	18
valid_sources[0x20]	52947	1			T72	15		T73	1		T214	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49382

1

T72

20

T73

2

T214

29

values[0x0]

all_enables

biggest_size

369077

1

T72

166

T73

17

T74

1

values[0x1]

all_enables

biggest_size

49114

1

T72

20

T73

1

T74

1