Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522005907	60650324	0	0
DepthKnown_A	522005907	521898876	0	0
RvalidKnown_A	522005907	521898876	0	0
WreadyKnown_A	522005907	521898876	0	0
gen_passthru_fifo.paramCheckPass	1019	1019	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	60650324	0	0
T1	92725	10028	0	0
T2	196593	26896	0	0
T3	104590	0	0	0
T4	348113	45279	0	0
T5	228447	30264	0	0
T6	391930	31206	0	0
T7	412156	158914	0	0
T44	134641	147118	0	0
T81	90818	8937	0	0
T82	108103	12560	0	0
T121	0	45279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522005907	46545669	0	0
DepthKnown_A	522005907	521898876	0	0
RvalidKnown_A	522005907	521898876	0	0
WreadyKnown_A	522005907	521898876	0	0
gen_passthru_fifo.paramCheckPass	1019	1019	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	46545669	0	0
T1	92725	8261	0	0
T2	196593	23081	0	0
T3	104590	0	0	0
T4	348113	42566	0	0
T5	228447	20480	0	0
T6	391930	23684	0	0
T7	412156	79825	0	0
T44	134641	128097	0	0
T81	90818	6735	0	0
T82	108103	10186	0	0
T121	0	42566	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522005907	43959905	0	0
DepthKnown_A	522005907	521898876	0	0
RvalidKnown_A	522005907	521898876	0	0
WreadyKnown_A	522005907	521898876	0	0
gen_passthru_fifo.paramCheckPass	1019	1019	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	43959905	0	0
T1	92725	6334	0	0
T2	196593	5180	0	0
T3	104590	39	0	0
T4	348113	34656	0	0
T5	228447	14429	0	0
T6	391930	18408	0	0
T7	412156	12943	0	0
T44	134641	185320	0	0
T81	90818	4674	0	0
T82	108103	6875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522005907	37016531	0	0
DepthKnown_A	522005907	521898876	0	0
RvalidKnown_A	522005907	521898876	0	0
WreadyKnown_A	522005907	521898876	0	0
gen_passthru_fifo.paramCheckPass	1019	1019	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	37016531	0	0
T1	92725	6219	0	0
T2	196593	4937	0	0
T3	104590	39	0	0
T4	348113	34511	0	0
T5	228447	14041	0	0
T6	391930	17900	0	0
T7	412156	11962	0	0
T44	134641	119907	0	0
T81	90818	4531	0	0
T82	108103	6729	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522005907	521898876	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611607155	91407	0	0
DepthKnown_A	611607155	611484027	0	0
RvalidKnown_A	611607155	611484027	0	0
WreadyKnown_A	611607155	611484027	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	91407	0	0
T1	92725	13	0	0
T2	196593	77	0	0
T3	104590	0	0	0
T4	348113	158	0	0
T5	228447	153	0	0
T6	391930	68	0	0
T7	412156	73	0	0
T44	134641	34	0	0
T81	90818	19	0	0
T82	108103	13	0	0
T121	0	158	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611607155	92367	0	0
DepthKnown_A	611607155	611484027	0	0
RvalidKnown_A	611607155	611484027	0	0
WreadyKnown_A	611607155	611484027	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	92367	0	0
T1	92725	13	0	0
T2	196593	77	0	0
T3	104590	0	0	0
T4	348113	158	0	0
T5	228447	153	0	0
T6	391930	68	0	0
T7	412156	73	0	0
T44	134641	34	0	0
T81	90818	19	0	0
T82	108103	13	0	0
T121	0	158	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611607155	53250	0	0
DepthKnown_A	611607155	611484027	0	0
RvalidKnown_A	611607155	611484027	0	0
WreadyKnown_A	611607155	611484027	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	53250	0	0
T1	92725	12	0	0
T2	196593	74	0	0
T3	104590	0	0	0
T4	348113	12	0	0
T5	228447	95	0	0
T6	391930	64	0	0
T7	412156	69	0	0
T44	134641	5	0	0
T81	90818	18	0	0
T82	108103	12	0	0
T121	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611607155	53250	0	0
DepthKnown_A	611607155	611484027	0	0
RvalidKnown_A	611607155	611484027	0	0
WreadyKnown_A	611607155	611484027	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	53250	0	0
T1	92725	12	0	0
T2	196593	74	0	0
T3	104590	0	0	0
T4	348113	12	0	0
T5	228447	95	0	0
T6	391930	64	0	0
T7	412156	69	0	0
T44	134641	5	0	0
T81	90818	18	0	0
T82	108103	12	0	0
T121	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611607155	38157	0	0
DepthKnown_A	611607155	611484027	0	0
RvalidKnown_A	611607155	611484027	0	0
WreadyKnown_A	611607155	611484027	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	38157	0	0
T1	92725	1	0	0
T2	196593	3	0	0
T3	104590	0	0	0
T4	348113	146	0	0
T5	228447	58	0	0
T6	391930	4	0	0
T7	412156	4	0	0
T44	134641	29	0	0
T81	90818	1	0	0
T82	108103	1	0	0
T121	0	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611607155	39117	0	0
DepthKnown_A	611607155	611484027	0	0
RvalidKnown_A	611607155	611484027	0	0
WreadyKnown_A	611607155	611484027	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	39117	0	0
T1	92725	1	0	0
T2	196593	3	0	0
T3	104590	0	0	0
T4	348113	146	0	0
T5	228447	58	0	0
T6	391930	4	0	0
T7	412156	4	0	0
T44	134641	29	0	0
T81	90818	1	0	0
T82	108103	1	0	0
T121	0	146	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611607155	611484027	0	0
T1	92725	92663	0	0
T2	196593	196538	0	0
T3	104590	104579	0	0
T4	348113	348055	0	0
T5	228447	228330	0	0
T6	391930	391591	0	0
T7	412156	412129	0	0
T44	134641	134635	0	0
T81	90818	90760	0	0
T82	108103	108041	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T44	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0