Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	419	1			T711	3		T751	1		T927	1
all_values[1]	444	1			T74	2		T547	1		T940	1
all_values[2]	475	1			T554	2		T711	1		T751	1
all_values[3]	415	1			T74	1		T908	1		T421	1
all_values[4]	414	1			T934	1		T547	1		T711	5
all_values[5]	420	1			T899	1		T421	1		T547	2
all_values[6]	419	1			T421	1		T934	1		T547	1
all_values[7]	425	1			T438	1		T908	1		T547	1
all_values[8]	442	1			T547	3		T554	1		T711	3
all_values[9]	449	1			T547	2		T711	4		T927	2
all_values[10]	402	1			T438	1		T711	2		T751	2
all_values[11]	427	1			T547	3		T554	1		T711	1
all_values[12]	406	1			T438	1		T421	1		T547	1
all_values[13]	430	1			T711	2		T751	2		T756	3
all_values[14]	451	1			T74	2		T438	1		T547	5
all_values[15]	452	1			T899	1		T547	2		T711	5
all_values[16]	432	1			T421	1		T547	1		T711	1
all_values[17]	458	1			T74	1		T554	2		T711	6
all_values[18]	440	1			T711	5		T751	3		T756	4
all_values[19]	433	1			T74	2		T711	1		T927	1
all_values[20]	420	1			T547	2		T711	1		T927	2
all_values[21]	440	1			T74	3		T547	2		T554	1
all_values[22]	448	1			T751	1		T470	1		T756	4
all_values[23]	434	1			T547	1		T711	2		T751	1
all_values[24]	402	1			T547	1		T711	2		T927	1
all_values[25]	433	1			T74	1		T547	1		T554	1
all_values[26]	473	1			T908	1		T547	2		T554	1
all_values[27]	423	1			T74	1		T438	1		T711	3
all_values[28]	472	1			T74	1		T547	1		T711	5
all_values[29]	417	1			T547	1		T711	3		T751	1
all_values[30]	402	1			T74	1		T547	1		T711	2
all_values[31]	448	1			T421	2		T934	1		T711	2
all_values[32]	434	1			T74	1		T547	1		T711	3
all_values[33]	442	1			T438	1		T547	4		T711	5
all_values[34]	451	1			T74	1		T547	1		T940	1
all_values[35]	429	1			T438	1		T711	3		T751	1
all_values[36]	421	1			T74	1		T254	1		T438	1
all_values[37]	426	1			T908	1		T547	4		T711	1
all_values[38]	451	1			T438	1		T421	1		T547	1
all_values[39]	442	1			T438	2		T547	2		T554	1
all_values[40]	487	1			T908	1		T547	2		T554	1
all_values[41]	450	1			T421	1		T547	2		T711	5
all_values[42]	437	1			T438	1		T547	1		T711	2
all_values[43]	404	1			T547	1		T554	2		T711	5
all_values[44]	460	1			T547	1		T711	1		T751	2
all_values[45]	438	1			T711	1		T927	1		T586	1
all_values[46]	464	1			T899	1		T547	2		T711	5
all_values[47]	425	1			T547	1		T711	2		T927	1
all_values[48]	476	1			T438	1		T421	1		T547	1
all_values[49]	416	1			T74	1		T547	1		T554	3