Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmBusIntegrity_A	0	0	130766330	0	0	0
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce1_A	0	0	130766330	0	0	976
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLockstepResetCountAlertCheck_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexPcMismatchCheck_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexRfEccErrCheck_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexStoreRespIntgErrCheck_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheck_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.NoReadyValidNoGrant_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	522617944	0	0	1010
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.NoReadyValidNoGrant_A	0	0	522617944	0	0	0
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmBusIntegrity_A	0	0	522617944	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.top_earlgrey.scanmodeKnown	0	0	530008001	530008001	0	0
tb.dut.top_earlgrey.u_pinmux_aon.AlertsKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.AonWkupReqKnownO_A	0	0	1643534	1447713	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTckKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTmsKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTrstKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DftStrapsKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DioKnownO_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.DioOeKnownO_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmRegWeOnehotCheck_A	0	0	130766330	6	0	0
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTckKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTmsKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTrstKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.MioKnownO_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.MioOeKnownO_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.PinmuxWkupStable_A	0	0	1643534	4144	0	0
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce0_A	0	0	130766330	1735	0	0
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTckKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTmsKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTrstKnown_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.TlAReadyKnownO_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.TlDValidKnownO_A	0	0	130766330	130079870	0	0
tb.dut.top_earlgrey.u_pinmux_aon.UsbWakeDetectActiveKnownO_A	0	0	1643534	1447713	0	0
tb.dut.top_earlgrey.u_pinmux_aon.UsbWkupReqKnownO_A	0	0	1643534	1447713	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A	0	0	130766330	40317066	0	280
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A	0	0	130766330	11973699	0	15
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A	0	0	130766330	1474	0	100
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A	0	0	130766330	1474	0	100
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSet_A	0	0	130766330	1474	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A	0	0	130766330	261	0	200
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff1_A	0	0	130766330	37359647	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.TapStrapKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap0_idxRange_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap1_idxRange_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap0_idxRange_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap1_idxRange_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tck_idxRange_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdi_idxRange_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdo_idxRange_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tms_idxRange_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.trst_idxRange_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.OutputsKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.FunctionCheck_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.OutputsKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.OutputsKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_no_flops.OutputDelay_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.OutputsKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_no_flops.OutputDelay_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.OutputsKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A	0	0	130766330	130072917	0	3033
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.OutputsKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A	0	0	130766330	130072917	0	3033
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.OutputsKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A	0	0	130766330	130072917	0	3033
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.OutputsKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A	0	0	130766330	130072917	0	3033
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.OutputsKnown_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_no_flops.OutputDelay_A	0	0	130766330	130079973	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown0	0	0	647	515	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown1	0	0	1774	762	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.en2addrHit	0	0	151076844	590361	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.reAfterRv	0	0	151076844	590361	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.rePulse	0	0	151076844	449081	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk.PayLoadWidthCheck	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.AllowedLatency_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.MatchedWidthAssert	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A	0	0	151076844	120852	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A	0	0	151076844	271	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	1856607	36	0	985
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	1856607	36	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	151076844	307	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	1856607	166	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	267	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	271	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.BusySrcReqChk_A	0	0	151076844	93382	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcAckBusyChk_A	0	0	151076844	238	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	238	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	238	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	238	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	238	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.BusySrcReqChk_A	0	0	151076844	88618	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcAckBusyChk_A	0	0	151076844	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.BusySrcReqChk_A	0	0	151076844	89602	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcAckBusyChk_A	0	0	151076844	227	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	227	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	227	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	227	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	227	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.BusySrcReqChk_A	0	0	151076844	83809	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcAckBusyChk_A	0	0	151076844	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	216	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.BusySrcReqChk_A	0	0	151076844	100180	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcAckBusyChk_A	0	0	151076844	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	254	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.BusySrcReqChk_A	0	0	151076844	93654	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcAckBusyChk_A	0	0	151076844	239	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	239	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	239	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	239	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	239	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.BusySrcReqChk_A	0	0	151076844	86171	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcAckBusyChk_A	0	0	151076844	220	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	220	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	220	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	220	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	220	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.BusySrcReqChk_A	0	0	151076844	82958	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcAckBusyChk_A	0	0	151076844	212	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	212	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	212	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	211	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	212	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.BusySrcReqChk_A	0	0	151076844	78398	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcAckBusyChk_A	0	0	151076844	200	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	200	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	200	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	199	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	200	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.BusySrcReqChk_A	0	0	151076844	99475	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcAckBusyChk_A	0	0	151076844	252	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	252	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	252	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	250	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	253	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.BusySrcReqChk_A	0	0	151076844	84577	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcAckBusyChk_A	0	0	151076844	217	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	217	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	217	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	217	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	217	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.BusySrcReqChk_A	0	0	151076844	95970	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcAckBusyChk_A	0	0	151076844	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.BusySrcReqChk_A	0	0	151076844	104162	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcAckBusyChk_A	0	0	151076844	264	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	264	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	264	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	264	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	264	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.BusySrcReqChk_A	0	0	151076844	100279	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcAckBusyChk_A	0	0	151076844	255	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	255	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	255	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	255	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	255	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.BusySrcReqChk_A	0	0	151076844	82447	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcAckBusyChk_A	0	0	151076844	212	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	212	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	212	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	212	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	212	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.BusySrcReqChk_A	0	0	151076844	96818	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcAckBusyChk_A	0	0	151076844	247	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	247	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	247	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	246	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	247	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.BusySrcReqChk_A	0	0	151076844	112643	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcAckBusyChk_A	0	0	151076844	284	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	284	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	284	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	283	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	287	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.BusySrcReqChk_A	0	0	151076844	89912	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcAckBusyChk_A	0	0	151076844	231	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	231	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	231	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	231	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	231	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.BusySrcReqChk_A	0	0	151076844	87360	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcAckBusyChk_A	0	0	151076844	224	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	224	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	224	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	224	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	224	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.BusySrcReqChk_A	0	0	151076844	88752	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcAckBusyChk_A	0	0	151076844	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	226	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.BusySrcReqChk_A	0	0	151076844	81877	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcAckBusyChk_A	0	0	151076844	209	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	209	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	209	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	209	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	210	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.BusySrcReqChk_A	0	0	151076844	103388	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcAckBusyChk_A	0	0	151076844	266	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	266	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	266	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	266	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	266	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.BusySrcReqChk_A	0	0	151076844	82428	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcAckBusyChk_A	0	0	151076844	210	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	210	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	210	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	210	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	210	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.BusySrcReqChk_A	0	0	151076844	96415	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.DstReqKnown_A	0	0	1856607	1631207	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcAckBusyChk_A	0	0	151076844	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcBusyKnown_A	0	0	151076844	150259008	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	151076844	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	1856607	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	1856607	243	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	151076844	244	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.wePulse	0	0	151076844	141280	0	0
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.WakeDetectActiveAonKnown_A	0	0	1643534	1447713	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable0_A	0	0	522617944	5	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A	0	0	522617944	25212767	0	88
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A	0	0	522617944	66603314	0	80
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A	0	0	522617944	451230788	0	2020
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A	0	0	522617944	451232682	0	1922
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexInstrIntgErrCheck_A	0	0	522617944	77	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLoadRespIntgErrCheck_A	0	0	522617944	589	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRegWeOnehotCheck_A	0	0	522617944	5	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_A	0	0	522617944	44423606	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DepthKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.RvalidKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.WreadyKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_A	0	0	522617944	37505106	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DepthKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.RvalidKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.WreadyKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_A	0	0	522617944	60566530	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DepthKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.RvalidKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.WreadyKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_A	0	0	522617944	46754476	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DepthKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.RvalidKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.WreadyKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_instr_intg_err_assert_signals.AssertConnected_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.g_rf_ecc_err_comb_assert_signals.AssertConnected_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	0	0	522617944	195	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	0	0	522617944	198	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.DontExceeedMaxReqs	0	0	522617944	44380040	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk.PayLoadWidthCheck	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.DontExceeedMaxReqs	0	0	522617944	60566530	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk.PayLoadWidthCheck	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckHotOne_A	0	0	522617944	513393065	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckNGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesReady_A	0	0	522617944	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesValid_A	0	0	522617944	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GrantKnown_A	0	0	522617944	513393065	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IdxKnown_A	0	0	522617944	513393065	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IndexIsCorrect_A	0	0	522617944	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.Priority_A	0	0	522617944	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReadyAndValidImplyGrant_A	0	0	522617944	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqAndReadyImplyGrant_A	0	0	522617944	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqImpliesValid_A	0	0	522617944	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ValidKnown_A	0	0	522617944	513393065	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A	0	0	522617944	3192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputDiffFromPrev_A	0	0	521967241	99324415	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputValid_A	0	0	522617944	4381	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	0	0	522617944	4381	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	0	0	522617944	4381	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	522617944	4381	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	522617944	4381	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckHotOne_A	0	0	522617944	513393065	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckNGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesReady_A	0	0	522617944	5192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesValid_A	0	0	522617944	5192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GrantKnown_A	0	0	522617944	513393065	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IdxKnown_A	0	0	522617944	513393065	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IndexIsCorrect_A	0	0	522617944	5192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.Priority_A	0	0	522617944	5192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReadyAndValidImplyGrant_A	0	0	522617944	5192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqAndReadyImplyGrant_A	0	0	522617944	5192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqImpliesValid_A	0	0	522617944	5192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ValidKnown_A	0	0	522617944	513393065	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A	0	0	522617944	5192	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.OutputsKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A	0	0	522617944	522502286	0	3030
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	0	0	522617944	48	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	0	0	522617944	48	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	129251916	48	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	522617944	48	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.NumCopiesMustBeGreaterZero_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.OutputsKnown_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A	0	0	522617944	522502286	0	3030
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.en2addrHit	0	0	604130077	37318	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.reAfterRv	0	0	604130077	37318	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.rePulse	0	0	604130077	29579	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk.PayLoadWidthCheck	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.AllowedLatency_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.MatchedWidthAssert	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_err.dataWidthOnly32_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.DataWidthCheck_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.NotOverflowed_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	604130077	93519	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	604130077	96426	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	604130077	52182	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	604130077	52181	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	604130077	41337	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	604130077	44245	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	604130077	604006200	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.maxN	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.wePulse	0	0	604130077	7739	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.DataWidthCheck_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.PayLoadWidthCheck	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmRegWeOnehotCheck_A	0	0	522617944	6	0	0
tb.dut.top_earlgrey.u_rv_plic.Irq0Tied_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_plic.IrqKnownO_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_plic.MsipKnownO_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_plic.TlAReadyKnownO_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_plic.TlDValidKnownO_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_irq_id_known[0].IrqIdKnownO_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputationInvalid_A	0	0	522617944	520664387	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputation_A	0	0	522617944	1845562	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputationInvalid_A	0	0	522617944	520664387	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputation_A	0	0	522617944	1845562	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.NumSources_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.ValidInImpliesValidOut_A	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_plic.onehot0Claim	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_plic.onehot0Complete	0	0	522617944	522509949	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.en2addrHit	0	0	604130077	220925	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.reAfterRv	0	0	604130077	220925	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.rePulse	0	0	604130077	151955	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk.PayLoadWidthCheck	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.AllowedLatency_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.MatchedWidthAssert	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	2932	2932	0	0
tb.dut.top_earlgrey.u_rv_plic.u_reg.wePulse	0	0	604130077	68970	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.FpvSecCmRegWeOnehotCheck_A	0	0	129251916	3	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.NumAlertsMatch_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr.IntrTKind_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr.IntrTKind_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.en2addrHit	0	0	129251916	5569	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.reAfterRv	0	0	129251916	5569	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.rePulse	0	0	129251916	4030	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk.PayLoadWidthCheck	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.AllowedLatency_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.MatchedWidthAssert	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1022	1022	0	0
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.wePulse	0	0	129251916	1539	0	0
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0	0	0	58	46	0	0
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1	0	0	147	132	0	0
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0	0	0	988	972	0	0
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1	0	0	1796	1776	0	0
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0	0	0	59	48	0	0
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1	0	0	113	99	0	0
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0	0	0	999	982	0	0
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1	0	0	132	119	0	0
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0	0	0	60	41	0	0
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1	0	0	150	140	0	0
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0	0	0	1283	1263	0	0
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1	0	0	163	153	0	0
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0	0	0	57	39	0	0
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1	0	0	131	116	0	0
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0	0	0	1281	1262	0	0
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1	0	0	563	548	0	0
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0	0	0	198	171	0	0
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1	0	0	825	797	0	0
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0	0	0	199	172	0	0
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1	0	0	819	791	0	0
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0	0	0	172	153	0	0
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1	0	0	26461	26429	0	0
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0	0	0	173	154	0	0
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1	0	0	26459	26427	0	0
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0	0	0	752	709	0	0
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1	0	0	26457	26425	0	0
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0	0	0	748	705	0	0
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1	0	0	26451	26419	0	0
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0	0	0	1823	1802	0	0
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1	0	0	828	802	0	0
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0	0	0	1823	1802	0	0
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1	0	0	832	806	0	0
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	1022	1022	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce1_A	0	0	130766330	0	0	976
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A	0	0	130766330	40317066	0	280
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A	0	0	130766330	11973699	0	15
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A	0	0	130766330	1474	0	100
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A	0	0	130766330	1474	0	100
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A	0	0	130766330	261	0	200
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A	0	0	130766330	130072917	0	3033
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A	0	0	130766330	130072917	0	3033
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A	0	0	130766330	130072917	0	3033
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A	0	0	130766330	130072917	0	3033
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	1856607	36	0	985
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A	0	0	522617944	25212767	0	88
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A	0	0	522617944	66603314	0	80
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A	0	0	522617944	451230788	0	2020
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A	0	0	522617944	451232682	0	1922
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	522617944	0	0	1010
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A	0	0	522617944	522502286	0	3030
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A	0	0	522617944	522502286	0	3030

Assertions Excluded:

ASSERTIONS	CATEGORY	SEVERITY	EXCLUSION	SRC
tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded
tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded
tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded
tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded
tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A	0	0	Excluded

	ASSERT	PROPERTIES	SEQUENCES
Total	572	0	0
Category 0	572	0	0

	ASSERT	PROPERTIES	SEQUENCES
Total	572	0	0
Severity 0	572	0	0

	NUMBER	PERCENT
Total Number	572	100.00
Uncovered	14	2.45
Success	553	96.68
Failure	0	0.00
Incomplete	18	3.15
Without Attempts	0	0.00
Excluded	5	0.87