Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	95.37	93.66	95.41		94.47	97.53	99.54

Total tests in report: 2932

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.68	39.68	38.53	38.53	39.12	39.12	46.66	46.66			55.58	55.58	58.04	58.04	0.14	0.14	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.269987485
49.31	9.63	43.92	5.39	54.69	15.57	46.99	0.33			65.50	9.92	83.22	25.17	1.53	1.39	/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.764169132
55.65	6.35	57.40	13.48	63.74	9.05	50.03	3.04			78.00	12.50	83.22	0.00	1.53	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1837814405
61.46	5.81	63.14	5.73	65.69	1.95	51.84	1.81			78.73	0.73	83.22	0.00	26.15	24.63	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1123710518
65.83	4.36	73.73	10.59	72.72	7.02	54.66	2.82			83.61	4.88	84.09	0.87	26.15	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3618899120
69.03	3.20	79.06	5.33	76.65	3.93	58.39	3.73			85.45	1.84	88.46	4.37	26.15	0.00	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2193680787
71.61	2.58	82.77	3.71	77.12	0.47	64.36	5.97			85.66	0.21	88.46	0.00	31.28	5.12	/workspace/coverage/cover_reg_top/80.xbar_error_random.4240703269
74.17	2.56	82.77	0.00	77.12	0.00	64.36	0.00			85.66	0.00	88.46	0.00	46.65	15.37	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2810942248
76.06	1.89	82.77	0.00	77.12	0.01	64.36	0.00			85.66	0.00	88.46	0.00	58.01	11.36	/workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2782897716
77.85	1.78	84.91	2.14	79.48	2.36	68.63	4.26			87.25	1.59	88.81	0.35	58.01	0.00	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4157935131
79.52	1.67	84.91	0.00	79.50	0.01	68.63	0.00			87.25	0.00	88.81	0.00	68.03	10.02	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.899700719
81.09	1.57	85.04	0.13	79.58	0.08	77.28	8.66			87.42	0.17	89.16	0.35	68.08	0.05	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.630565333
82.31	1.22	85.04	0.00	79.73	0.15	77.28	0.00			87.44	0.02	89.16	0.00	75.21	7.13	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.2846019804
83.36	1.05	86.11	1.07	79.84	0.12	77.91	0.63			87.44	0.00	89.16	0.00	79.67	4.46	/workspace/coverage/cover_reg_top/66.xbar_access_same_device.2684633770
84.40	1.04	87.22	1.11	80.66	0.82	80.72	2.80			88.37	0.93	89.69	0.52	79.72	0.05	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4061764057
85.32	0.92	88.46	1.24	81.67	1.01	82.78	2.06			89.59	1.22	89.69	0.00	79.72	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1550643016
86.20	0.88	89.25	0.79	82.51	0.84	84.19	1.41			90.19	0.60	89.69	0.00	81.39	1.67	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1696340109
87.06	0.86	90.00	0.75	82.77	0.26	84.20	0.01			90.49	0.30	93.53	3.85	81.39	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.495956573
87.81	0.75	91.01	1.01	83.63	0.87	84.40	0.20			91.32	0.83	95.10	1.57	81.39	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.587919109
88.54	0.73	91.01	0.00	83.63	0.00	84.40	0.00			91.32	0.00	95.10	0.00	85.76	4.37	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2673264235
89.14	0.60	91.01	0.01	84.11	0.48	84.43	0.03			91.37	0.05	95.10	0.00	88.80	3.04	/workspace/coverage/cover_reg_top/38.xbar_stress_all.3441483285
89.68	0.54	91.53	0.52	84.55	0.44	86.25	1.82			91.83	0.46	95.10	0.00	88.80	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2427809037
90.19	0.51	91.53	0.00	84.55	0.00	86.25	0.00			91.83	0.00	95.10	0.00	91.87	3.07	/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.600041267
90.67	0.48	92.14	0.61	86.28	1.72	86.38	0.13			92.08	0.25	95.10	0.00	92.01	0.14	/workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.16061593
91.03	0.36	92.68	0.54	86.99	0.71	86.71	0.32			92.67	0.59	95.10	0.00	92.01	0.00	/workspace/coverage/default/2.chip_sw_gpio.874023866
91.38	0.35	92.68	0.00	87.00	0.01	86.71	0.00			92.67	0.00	95.10	0.00	94.13	2.11	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2044797422
91.68	0.30	93.15	0.46	87.49	0.49	87.35	0.65			92.89	0.22	95.10	0.00	94.13	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.87831467
91.98	0.30	93.15	0.01	89.17	1.68	87.35	0.00			92.89	0.00	95.10	0.00	94.21	0.08	/workspace/coverage/cover_reg_top/27.chip_tl_errors.1833172148
92.26	0.28	93.15	0.00	89.18	0.01	87.35	0.00			92.89	0.00	95.10	0.00	95.85	1.64	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.439073142
92.53	0.27	93.15	0.00	89.18	0.00	88.98	1.63			92.89	0.00	95.10	0.00	95.85	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2972050923
92.80	0.27	93.35	0.20	89.37	0.19	89.25	0.27			92.97	0.08	95.98	0.87	95.85	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2061367279
93.01	0.21	93.56	0.21	89.54	0.17	89.63	0.38			93.13	0.15	96.33	0.35	95.85	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2985044122
93.18	0.17	93.68	0.12	89.57	0.03	90.45	0.81			93.15	0.02	96.33	0.00	95.91	0.06	/workspace/coverage/default/1.chip_jtag_csr_rw.804082749
93.33	0.15	93.73	0.05	89.63	0.06	90.84	0.40			93.15	0.00	96.33	0.00	96.31	0.40	/workspace/coverage/default/2.chip_sw_alert_test.3523606118
93.48	0.15	93.73	0.00	89.63	0.00	91.73	0.89			93.15	0.00	96.33	0.00	96.31	0.00	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1419263615
93.63	0.15	93.73	0.00	90.51	0.89	91.73	0.00			93.15	0.00	96.33	0.00	96.31	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.100728623
93.76	0.14	93.90	0.17	90.57	0.05	92.26	0.52			93.18	0.02	96.33	0.00	96.36	0.05	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2585361666
93.90	0.13	93.94	0.04	90.92	0.35	92.29	0.03			93.55	0.37	96.33	0.00	96.36	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3868111001
94.01	0.11	93.94	0.00	90.94	0.02	92.29	0.00			93.55	0.00	96.33	0.00	97.02	0.66	/workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3217627757
94.11	0.10	93.94	0.00	90.94	0.00	92.29	0.00			93.55	0.00	96.33	0.00	97.63	0.61	/workspace/coverage/cover_reg_top/95.xbar_access_same_device.3472343238
94.21	0.10	93.95	0.01	90.99	0.05	92.62	0.33			93.57	0.02	96.50	0.17	97.63	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4068742149
94.29	0.08	93.95	0.00	91.00	0.01	93.11	0.50			93.57	0.00	96.50	0.00	97.63	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.371479080
94.37	0.08	93.95	0.00	91.23	0.23	93.11	0.00			93.83	0.26	96.50	0.00	97.63	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3210718330
94.45	0.07	94.08	0.12	91.34	0.11	93.21	0.09			93.92	0.10	96.50	0.00	97.63	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3010413956
94.51	0.07	94.08	0.00	91.34	0.00	93.60	0.40			93.92	0.00	96.50	0.00	97.63	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1227317950
94.57	0.05	94.08	0.00	91.35	0.02	93.60	0.00			93.92	0.00	96.50	0.00	97.93	0.31	/workspace/coverage/cover_reg_top/50.xbar_stress_all.423871247
94.62	0.05	94.08	0.00	91.35	0.00	93.90	0.30			93.92	0.00	96.50	0.00	97.93	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1321581542
94.66	0.04	94.10	0.03	91.38	0.02	93.90	0.01			93.95	0.02	96.68	0.17	97.94	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.287231474
94.70	0.04	94.10	0.00	91.55	0.17	93.90	0.00			94.00	0.05	96.68	0.00	97.99	0.05	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3226306625
94.74	0.04	94.13	0.02	91.57	0.02	93.90	0.00			94.01	0.02	96.85	0.17	98.00	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1635720497
94.78	0.04	94.19	0.06	91.65	0.08	93.92	0.02			94.09	0.07	96.85	0.00	98.00	0.00	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2765493418
94.82	0.04	94.20	0.01	91.67	0.01	93.92	0.00			94.11	0.02	97.03	0.17	98.01	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.846627899
94.86	0.04	94.20	0.01	91.68	0.01	93.94	0.02			94.12	0.01	97.20	0.17	98.03	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.999585859
94.90	0.04	94.21	0.01	91.87	0.19	93.94	0.01			94.13	0.02	97.20	0.00	98.03	0.00	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3164396185
94.93	0.04	94.21	0.00	91.93	0.05	93.94	0.00			94.13	0.00	97.20	0.00	98.19	0.16	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2046140880
94.97	0.04	94.21	0.01	91.94	0.01	93.94	0.01			94.14	0.01	97.38	0.17	98.20	0.01	/workspace/coverage/default/61.chip_sw_all_escalation_resets.2647955921
95.00	0.03	94.21	0.00	92.14	0.20	93.94	0.00			94.14	0.00	97.38	0.00	98.20	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.960458433
95.04	0.03	94.21	0.00	92.34	0.20	93.94	0.00			94.14	0.00	97.38	0.00	98.20	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.438592314
95.07	0.03	94.21	0.00	92.34	0.00	94.11	0.17			94.14	0.00	97.38	0.00	98.24	0.04	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3249075885
95.10	0.03	94.25	0.03	92.40	0.05	94.18	0.07			94.18	0.04	97.38	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3386142984
95.14	0.03	94.25	0.00	92.40	0.01	94.33	0.15			94.18	0.00	97.38	0.00	98.27	0.04	/workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1193093847
95.17	0.03	94.26	0.01	92.49	0.08	94.33	0.00			94.28	0.10	97.38	0.00	98.27	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1456740261
95.20	0.03	94.33	0.07	92.52	0.03	94.36	0.03			94.33	0.05	97.38	0.00	98.27	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.558483994
95.23	0.03	94.33	0.00	92.52	0.00	94.36	0.01			94.33	0.00	97.55	0.17	98.27	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1953476051
95.25	0.03	94.33	0.00	92.52	0.00	94.53	0.17			94.33	0.00	97.55	0.00	98.27	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1112553760
95.28	0.03	94.40	0.07	92.52	0.00	94.61	0.08			94.34	0.01	97.55	0.00	98.27	0.00	/workspace/coverage/default/3.chip_tap_straps_rma.2587651133
95.31	0.02	94.47	0.07	92.57	0.05	94.61	0.00			94.37	0.03	97.55	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.4146580650
95.33	0.02	94.53	0.07	92.61	0.05	94.61	0.00			94.39	0.02	97.55	0.00	98.27	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.561488973
95.35	0.02	94.53	0.00	92.62	0.01	94.61	0.00			94.39	0.00	97.55	0.00	98.39	0.12	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2698939586
95.37	0.02	94.53	0.00	92.73	0.12	94.61	0.00			94.39	0.00	97.55	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.513717004
95.38	0.02	94.56	0.03	92.77	0.04	94.62	0.01			94.41	0.02	97.55	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.728200033
95.40	0.02	94.56	0.00	92.77	0.00	94.72	0.10			94.41	0.00	97.55	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3820703418
95.42	0.02	94.56	0.00	92.77	0.00	94.82	0.10			94.41	0.00	97.55	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.134105814
95.43	0.02	94.60	0.03	92.79	0.02	94.84	0.02			94.42	0.01	97.55	0.00	98.40	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.1713518790
95.45	0.02	94.60	0.00	92.79	0.00	94.84	0.00			94.42	0.00	97.55	0.00	98.50	0.09	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1542380610
95.46	0.02	94.60	0.00	92.88	0.09	94.84	0.00			94.42	0.00	97.55	0.00	98.50	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.137669682
95.48	0.01	94.60	0.01	92.88	0.00	94.91	0.07			94.43	0.01	97.55	0.00	98.50	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1175566091
95.49	0.01	94.61	0.01	92.92	0.03	94.96	0.05			94.43	0.00	97.55	0.00	98.50	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.328704763
95.51	0.01	94.61	0.00	92.98	0.07	94.96	0.00			94.43	0.00	97.55	0.00	98.51	0.01	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1422129941
95.52	0.01	94.61	0.00	93.01	0.03	94.96	0.00			94.43	0.00	97.55	0.00	98.55	0.05	/workspace/coverage/cover_reg_top/16.xbar_stress_all.1045879598
95.53	0.01	94.61	0.00	93.08	0.07	94.96	0.00			94.43	0.00	97.55	0.00	98.55	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.881836526
95.54	0.01	94.61	0.00	93.09	0.01	95.01	0.05			94.43	0.00	97.55	0.00	98.57	0.01	/workspace/coverage/default/1.rom_e2e_shutdown_output.2508064514
95.55	0.01	94.64	0.03	93.10	0.02	95.02	0.01			94.43	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/9.chip_csr_rw.1768329431
95.56	0.01	94.64	0.00	93.14	0.04	95.02	0.00			94.43	0.00	97.55	0.00	98.58	0.01	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2394217691
95.57	0.01	94.66	0.02	93.15	0.01	95.03	0.01			94.44	0.02	97.55	0.00	98.58	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3439279756
95.58	0.01	94.68	0.02	93.16	0.01	95.03	0.01			94.46	0.02	97.55	0.00	98.58	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2335295393
95.58	0.01	94.68	0.00	93.21	0.05	95.03	0.00			94.46	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.3128851308
95.59	0.01	94.68	0.00	93.21	0.00	95.08	0.05			94.46	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2509221894
95.60	0.01	94.68	0.00	93.21	0.00	95.12	0.05			94.46	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3183716210
95.61	0.01	94.68	0.00	93.25	0.04	95.12	0.00			94.46	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3387071068
95.61	0.01	94.68	0.00	93.25	0.01	95.12	0.00			94.46	0.00	97.55	0.00	98.61	0.04	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.771230654
95.62	0.01	94.68	0.00	93.26	0.01	95.12	0.00			94.46	0.00	97.55	0.00	98.65	0.04	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.511203484
95.63	0.01	94.68	0.00	93.26	0.00	95.16	0.04			94.46	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1444437671
95.63	0.01	94.70	0.02	93.27	0.01	95.17	0.01			94.46	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3066947521
95.64	0.01	94.70	0.00	93.30	0.04	95.17	0.00			94.46	0.00	97.55	0.00	98.65	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1313540074
95.64	0.01	94.70	0.00	93.30	0.00	95.17	0.00			94.46	0.00	97.55	0.00	98.68	0.04	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1185282871
95.65	0.01	94.70	0.00	93.30	0.00	95.17	0.00			94.46	0.00	97.55	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.4214591188
95.66	0.01	94.72	0.02	93.30	0.00	95.18	0.01			94.46	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.1510506047
95.66	0.01	94.72	0.00	93.30	0.00	95.21	0.03			94.46	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1741063626
95.67	0.01	94.72	0.00	93.33	0.03	95.21	0.00			94.46	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all.184739812
95.67	0.01	94.72	0.00	93.36	0.03	95.21	0.00			94.46	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.2148183595
95.68	0.01	94.73	0.01	93.38	0.02	95.21	0.00			94.46	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx.2676894788
95.68	0.01	94.73	0.00	93.38	0.00	95.24	0.03			94.46	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.4067203162
95.69	0.01	94.73	0.00	93.38	0.00	95.27	0.03			94.46	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3578621202
95.69	0.01	94.73	0.00	93.41	0.02	95.27	0.00			94.46	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3357884988
95.69	0.01	94.73	0.00	93.43	0.02	95.27	0.00			94.46	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2962213063
95.70	0.01	94.73	0.00	93.43	0.00	95.27	0.00			94.46	0.00	97.55	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.143377094
95.70	0.01	94.73	0.01	93.44	0.01	95.27	0.01			94.46	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.520567871
95.70	0.01	94.73	0.00	93.44	0.00	95.29	0.02			94.46	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/default/1.chip_sw_flash_init.3345041894
95.71	0.01	94.74	0.01	93.45	0.01	95.30	0.01			94.46	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.618358425
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95.71	0.01	94.74	0.00	93.48	0.02	95.30	0.00			94.46	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_gpio.2321948170
95.72	0.01	94.74	0.00	93.48	0.00	95.31	0.02			94.46	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2599177260
95.72	0.01	94.74	0.00	93.49	0.01	95.31	0.00			94.46	0.00	97.55	0.00	98.75	0.01	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.2201852547
95.72	0.01	94.74	0.01	93.49	0.00	95.33	0.01			94.46	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2159332301
95.72	0.01	94.74	0.00	93.50	0.01	95.33	0.00			94.46	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3492775638
95.73	0.01	94.74	0.00	93.52	0.01	95.33	0.00			94.46	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1581195467
95.73	0.01	94.75	0.01	93.52	0.01	95.33	0.00			94.46	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2745379914
95.73	0.01	94.75	0.00	93.52	0.00	95.33	0.01			94.47	0.01	97.55	0.00	98.75	0.00	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2811167740
95.73	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.77	0.01	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.36603540
95.73	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/25.chip_tl_errors.2510897681
95.74	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.754117916
95.74	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.963475574
95.74	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2820170300
95.74	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.879925685
95.74	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2320378902
95.75	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3867619854
95.75	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325404228
95.75	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2140371554
95.75	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2057765192
95.75	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2615831898
95.76	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.2629316169
95.76	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3073973071
95.76	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1800198506
95.76	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.844164933
95.76	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1421683978
95.76	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3547905741
95.77	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3762980016
95.77	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2783908761
95.77	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1126702028
95.77	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1077321018
95.77	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3204907833
95.78	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3459371190
95.78	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4186164496
95.78	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2633523565
95.78	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.848489787
95.78	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3045882244
95.79	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3179423763
95.79	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3955020781
95.79	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1695446450
95.79	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1788811964
95.79	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3401944113
95.80	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3410027958
95.80	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.2739352834
95.80	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2340555778
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95.80	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1103908478
95.81	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.21	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3687018504
95.81	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.22	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3190485976
95.81	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.24	0.01	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3649731507
95.81	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.25	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3569723966
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95.82	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.27	0.01	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2615276463
95.82	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.28	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1136810164
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95.85	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.46	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2241940922
95.85	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1031133565
95.85	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985951161
95.85	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.3848420231
95.85	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/91.chip_sw_all_escalation_resets.663775040
95.86	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1128913774
95.86	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.3450649522
95.86	0.01	94.75	0.00	93.52	0.00	95.33	0.00			94.47	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/99.chip_sw_all_escalation_resets.813005435
95.86	0.01	94.75	0.00	93.53	0.01	95.33	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all.1090124104
95.86	0.01	94.75	0.00	93.54	0.01	95.33	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1531229944
95.87	0.01	94.75	0.00	93.55	0.01	95.33	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2644444017
95.87	0.01	94.75	0.00	93.57	0.01	95.33	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2064868022
95.87	0.01	94.75	0.00	93.58	0.01	95.33	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.502012423
95.87	0.01	94.75	0.00	93.59	0.01	95.33	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3146886087
95.87	0.01	94.75	0.01	93.59	0.00	95.34	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/57.chip_sw_all_escalation_resets.4152771232
95.87	0.01	94.76	0.01	93.59	0.01	95.34	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4221032327
95.88	0.01	94.77	0.01	93.59	0.01	95.34	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.2615971312
95.88	0.01	94.78	0.01	93.59	0.00	95.34	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1720556788
95.88	0.01	94.78	0.00	93.59	0.00	95.35	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.31864251
95.88	0.01	94.78	0.00	93.60	0.01	95.35	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2739298790
95.88	0.01	94.78	0.00	93.60	0.00	95.35	0.00			94.47	0.01	97.55	0.00	99.54	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.3330241651
95.88	0.01	94.78	0.00	93.60	0.01	95.35	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.2704349645
95.89	0.01	94.78	0.00	93.61	0.01	95.35	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3009186715
95.89	0.01	94.78	0.00	93.62	0.01	95.35	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3974639863
95.89	0.01	94.78	0.00	93.62	0.00	95.36	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4142626602
95.89	0.01	94.78	0.00	93.62	0.00	95.36	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_kmac_entropy.3155503706
95.89	0.01	94.78	0.00	93.62	0.00	95.37	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.678544440
95.89	0.01	94.79	0.01	93.62	0.00	95.37	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.181941812
95.89	0.01	94.79	0.00	93.62	0.00	95.38	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3248095588
95.89	0.01	94.79	0.00	93.62	0.00	95.38	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3272809357
95.89	0.01	94.79	0.00	93.62	0.00	95.39	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2452379148
95.89	0.01	94.79	0.00	93.62	0.00	95.39	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3481896428
95.89	0.01	94.79	0.00	93.62	0.00	95.40	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.756156317
95.90	0.01	94.79	0.00	93.62	0.00	95.40	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2785247163
95.90	0.01	94.79	0.00	93.62	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all.3140095180
95.90	0.01	94.79	0.00	93.63	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.3324254610
95.90	0.01	94.79	0.00	93.63	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/17.xbar_access_same_device.3633145351
95.90	0.01	94.79	0.00	93.63	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/22.xbar_error_random.1062981225
95.90	0.01	94.79	0.00	93.64	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2065487886
95.90	0.01	94.79	0.00	93.64	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2017275526
95.90	0.01	94.79	0.00	93.64	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1601506223
95.90	0.01	94.79	0.00	93.65	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.918062902
95.90	0.01	94.79	0.00	93.65	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3245420783
95.90	0.01	94.79	0.00	93.65	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.46679754
95.90	0.01	94.79	0.00	93.66	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.169356282
95.90	0.01	94.79	0.00	93.66	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1259590262
95.90	0.01	94.79	0.00	93.66	0.01	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4172139986
95.90	0.01	94.79	0.00	93.66	0.00	95.40	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.4209103772
95.90	0.01	94.79	0.01	93.66	0.00	95.40	0.00			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2504351018
95.90	0.01	94.79	0.00	93.66	0.00	95.41	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2007078825
95.91	0.01	94.79	0.00	93.66	0.00	95.41	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3666295139
95.91	0.01	94.79	0.00	93.66	0.00	95.41	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2170207374
95.91	0.01	94.79	0.00	93.66	0.00	95.41	0.01			94.47	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1380060420

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2988703012
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1124725823
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1208818295
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1310050982
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3157623806
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2293664621
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1193672842
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1684368709
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1064362976
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1846596190
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1159377544
/workspace/coverage/cover_reg_top/0.xbar_error_random.1651925913
/workspace/coverage/cover_reg_top/0.xbar_random.1312516447
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2614246908
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1913653763
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.323935525
/workspace/coverage/cover_reg_top/0.xbar_same_source.930792794
/workspace/coverage/cover_reg_top/0.xbar_smoke.2656679711
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2957539317
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3833797430
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1273011843
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3182465664
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.122783431
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2718390556
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2826724318
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.191106036
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3427744144
/workspace/coverage/cover_reg_top/1.chip_csr_rw.494644801
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2810112697
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.76430079
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1244756430
/workspace/coverage/cover_reg_top/1.chip_tl_errors.339188923
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.464195880
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3239722691
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1910280717
/workspace/coverage/cover_reg_top/1.xbar_error_random.2900182468
/workspace/coverage/cover_reg_top/1.xbar_random.2407264567
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2390310926
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4011381980
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.440507711
/workspace/coverage/cover_reg_top/1.xbar_same_source.125982846
/workspace/coverage/cover_reg_top/1.xbar_smoke.250216838
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2196753108
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1480326820
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1280475521
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1324487172
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3757806193
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2427384942
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.894704476
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3638162395
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3624808318
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2552021493
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1517853267
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2520655522
/workspace/coverage/cover_reg_top/10.xbar_error_random.4049859720
/workspace/coverage/cover_reg_top/10.xbar_random.3859626015
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.291257390
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3632144504
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1352153801
/workspace/coverage/cover_reg_top/10.xbar_same_source.305262008
/workspace/coverage/cover_reg_top/10.xbar_smoke.844078482
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.29031642
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.510012406
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.356403444
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1178249611
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3449281467
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2849870943
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.404753201
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.420724594
/workspace/coverage/cover_reg_top/11.chip_csr_rw.478347828
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3636922365
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1777161385
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2706202761
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1822294005
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2622495547
/workspace/coverage/cover_reg_top/11.xbar_error_random.4163878559
/workspace/coverage/cover_reg_top/11.xbar_random.1248369052
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3175248704
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.586034649
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1115581434
/workspace/coverage/cover_reg_top/11.xbar_same_source.102202241
/workspace/coverage/cover_reg_top/11.xbar_smoke.908506479
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4014653429
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2346908902
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3466531012
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3635465358
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.689249333
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3690639094
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2177639659
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1758866072
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2157866284
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1720041049
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1683639428
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1077690897
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3980738540
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2993681071
/workspace/coverage/cover_reg_top/12.xbar_error_random.1420388798
/workspace/coverage/cover_reg_top/12.xbar_random.3256237698
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4059212847
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.215867834
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3787455068
/workspace/coverage/cover_reg_top/12.xbar_same_source.3884248834
/workspace/coverage/cover_reg_top/12.xbar_smoke.274168958
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2996623910
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.42614168
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1258272500
/workspace/coverage/cover_reg_top/12.xbar_stress_all.4145901409
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4094676563
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1704952693
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2136260633
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3216940256
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/workspace/coverage/default/30.chip_sw_all_escalation_resets.947334889
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3501420264
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1483731550
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1588226417
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2097366677
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.732990256
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/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1292674110
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/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4093950166
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/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.865458057
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/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4039606052
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1833593213
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3235861540
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3128936908
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2972799504
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3635171221
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3513247178
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2387727894
/workspace/coverage/default/53.chip_sw_all_escalation_resets.4038890873
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/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3611970481
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/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1002867229
/workspace/coverage/default/58.chip_sw_all_escalation_resets.609559318
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/workspace/coverage/default/6.chip_sw_all_escalation_resets.716104650
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/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1779440544
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.269720205
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/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1424943763
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/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3502677262
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/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1693863733
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3085570277
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/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3728993516
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2085500520
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3187471976
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172548265
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/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3415834778
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/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1374377480
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/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3054600423
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/workspace/coverage/default/8.chip_sw_all_escalation_resets.3766487831
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/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1894616218
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/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2465035676
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/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2729196945
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3142093859
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1814408969
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1561243451
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2195663572
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3722456814
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1771181416
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2106582466
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4208457238
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3786130492
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3312738956
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2293692175
/workspace/coverage/default/92.chip_sw_all_escalation_resets.774268492
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1389198632
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2013467495
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2761687868
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1972180315
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2640838707
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.174428050
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1177625858
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1880958590
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.725934641
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2407973051
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3368976498
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2908096363

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Total test records in report: 2932

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1801484867			Jul 24 08:24:32 PM PDT 24	Jul 24 08:31:00 PM PDT 24	3293283550 ps
T2	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2782189420			Jul 24 08:03:09 PM PDT 24	Jul 24 08:17:47 PM PDT 24	4631199568 ps
T3	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.761704829			Jul 24 07:56:33 PM PDT 24	Jul 24 08:01:31 PM PDT 24	3642071540 ps
T33	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.269987485			Jul 24 07:59:40 PM PDT 24	Jul 24 08:14:55 PM PDT 24	5621903000 ps
T34	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2811167740			Jul 24 08:08:11 PM PDT 24	Jul 24 08:15:12 PM PDT 24	4704618696 ps
T35	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.4287934645			Jul 24 08:07:46 PM PDT 24	Jul 24 08:41:20 PM PDT 24	9203898004 ps
T86	/workspace/coverage/default/1.chip_sw_hmac_multistream.856671698			Jul 24 08:08:40 PM PDT 24	Jul 24 08:41:06 PM PDT 24	7608461708 ps
T60	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2626980988			Jul 24 07:57:43 PM PDT 24	Jul 24 08:07:25 PM PDT 24	6262440174 ps
T87	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.558483994			Jul 24 08:04:39 PM PDT 24	Jul 24 08:18:57 PM PDT 24	5518210856 ps
T88	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3929663028			Jul 24 08:17:05 PM PDT 24	Jul 24 08:26:56 PM PDT 24	3484533944 ps
T9	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3618899120			Jul 24 08:01:43 PM PDT 24	Jul 24 08:06:49 PM PDT 24	3343789628 ps
T6	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1321581542			Jul 24 08:15:42 PM PDT 24	Jul 24 08:27:15 PM PDT 24	6772745638 ps
T4	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2585361666			Jul 24 08:25:20 PM PDT 24	Jul 24 08:34:29 PM PDT 24	5586098364 ps
T7	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3172158961			Jul 24 08:23:18 PM PDT 24	Jul 24 08:31:07 PM PDT 24	6013141951 ps
T166	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2831463121			Jul 24 08:15:42 PM PDT 24	Jul 24 08:50:13 PM PDT 24	12447254552 ps
T8	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2972050923			Jul 24 08:09:34 PM PDT 24	Jul 24 09:21:08 PM PDT 24	43617304992 ps
T5	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2765493418			Jul 24 08:24:12 PM PDT 24	Jul 24 09:01:06 PM PDT 24	12881468116 ps
T127	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.87831467			Jul 24 07:58:50 PM PDT 24	Jul 24 08:06:11 PM PDT 24	5406858312 ps
T115	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4061764057			Jul 24 08:26:05 PM PDT 24	Jul 24 09:12:14 PM PDT 24	22553953991 ps
T450	/workspace/coverage/default/2.rom_keymgr_functest.3911882592			Jul 24 08:17:51 PM PDT 24	Jul 24 08:28:42 PM PDT 24	4789242384 ps
T118	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.565763560			Jul 24 08:18:34 PM PDT 24	Jul 24 08:36:25 PM PDT 24	7385730508 ps
T373	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3974904827			Jul 24 08:23:41 PM PDT 24	Jul 24 08:32:02 PM PDT 24	4633729288 ps
T61	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3725476779			Jul 24 08:28:27 PM PDT 24	Jul 24 08:38:02 PM PDT 24	5894928550 ps
T218	/workspace/coverage/default/47.chip_sw_all_escalation_resets.1713518790			Jul 24 08:27:02 PM PDT 24	Jul 24 08:35:49 PM PDT 24	5281848360 ps
T247	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3848760405			Jul 24 08:16:35 PM PDT 24	Jul 24 08:22:23 PM PDT 24	4403581158 ps
T119	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4068742149			Jul 24 08:07:40 PM PDT 24	Jul 24 08:17:11 PM PDT 24	3980469326 ps
T65	/workspace/coverage/default/2.chip_tap_straps_prod.675364988			Jul 24 08:20:38 PM PDT 24	Jul 24 08:23:09 PM PDT 24	2484085110 ps
T294	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1913087017			Jul 24 08:05:07 PM PDT 24	Jul 24 08:10:10 PM PDT 24	3214957460 ps
T213	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.519309451			Jul 24 08:24:04 PM PDT 24	Jul 24 08:59:29 PM PDT 24	12598075800 ps
T295	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.677094992			Jul 24 08:14:35 PM PDT 24	Jul 24 08:19:57 PM PDT 24	2949571456 ps
T67	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1458680197			Jul 24 08:02:44 PM PDT 24	Jul 24 08:50:02 PM PDT 24	24299170186 ps
T15	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3728993516			Jul 24 08:23:24 PM PDT 24	Jul 24 08:45:58 PM PDT 24	8278276040 ps
T202	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4207311337			Jul 24 08:00:51 PM PDT 24	Jul 24 08:05:10 PM PDT 24	2963613883 ps
T185	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2488051076			Jul 24 08:14:37 PM PDT 24	Jul 24 08:21:59 PM PDT 24	3808505944 ps
T16	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2006038134			Jul 24 08:00:27 PM PDT 24	Jul 24 08:04:36 PM PDT 24	3161748952 ps
T48	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4157935131			Jul 24 08:24:11 PM PDT 24	Jul 24 09:20:31 PM PDT 24	15079128314 ps
T120	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2432810493			Jul 24 07:57:56 PM PDT 24	Jul 24 07:59:40 PM PDT 24	1999906836 ps
T124	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.781851572			Jul 24 08:01:00 PM PDT 24	Jul 24 08:15:18 PM PDT 24	8076412800 ps
T125	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2730862712			Jul 24 08:14:06 PM PDT 24	Jul 24 08:21:46 PM PDT 24	7537167320 ps
T412	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1374377480			Jul 24 08:33:45 PM PDT 24	Jul 24 08:44:29 PM PDT 24	4195661128 ps
T215	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2222633689			Jul 24 08:11:39 PM PDT 24	Jul 24 08:21:30 PM PDT 24	4239287384 ps
T263	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1419263615			Jul 24 08:22:08 PM PDT 24	Jul 24 09:20:50 PM PDT 24	17631856508 ps
T219	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1008699341			Jul 24 07:59:17 PM PDT 24	Jul 24 08:12:19 PM PDT 24	4508380100 ps
T66	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.630565333			Jul 24 08:04:39 PM PDT 24	Jul 24 09:47:25 PM PDT 24	48468033240 ps
T413	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.395281252			Jul 24 08:29:15 PM PDT 24	Jul 24 08:33:28 PM PDT 24	3254129000 ps
T12	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2061367279			Jul 24 08:15:20 PM PDT 24	Jul 24 08:23:28 PM PDT 24	3914496600 ps
T754	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.520401088			Jul 24 08:25:25 PM PDT 24	Jul 24 08:33:40 PM PDT 24	4010918060 ps
T209	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2809060775			Jul 24 07:57:22 PM PDT 24	Jul 24 08:29:03 PM PDT 24	8769003780 ps
T203	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2250160118			Jul 24 08:15:13 PM PDT 24	Jul 24 08:19:52 PM PDT 24	3369261812 ps
T797	/workspace/coverage/default/1.chip_sw_aes_enc.2253994614			Jul 24 08:05:37 PM PDT 24	Jul 24 08:10:00 PM PDT 24	2843048976 ps
T68	/workspace/coverage/default/1.chip_jtag_csr_rw.804082749			Jul 24 07:59:38 PM PDT 24	Jul 24 08:18:24 PM PDT 24	11056478840 ps
T329	/workspace/coverage/default/0.chip_sw_otbn_randomness.190350049			Jul 24 07:59:36 PM PDT 24	Jul 24 08:15:18 PM PDT 24	6040443760 ps
T18	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3010413956			Jul 24 08:02:52 PM PDT 24	Jul 24 08:26:09 PM PDT 24	23447380788 ps
T106	/workspace/coverage/default/1.chip_sw_power_sleep_load.611172686			Jul 24 08:09:12 PM PDT 24	Jul 24 08:15:55 PM PDT 24	4335523560 ps
T107	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2452379148			Jul 24 07:59:46 PM PDT 24	Jul 24 09:36:18 PM PDT 24	49455791392 ps
T108	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3939310841			Jul 24 08:08:29 PM PDT 24	Jul 24 08:13:00 PM PDT 24	2473642988 ps
T109	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1948418734			Jul 24 07:58:36 PM PDT 24	Jul 24 08:02:38 PM PDT 24	2512773944 ps
T53	/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1451657518			Jul 24 08:11:37 PM PDT 24	Jul 24 08:17:42 PM PDT 24	3293323769 ps
T110	/workspace/coverage/default/1.chip_sw_example_flash.2072730500			Jul 24 08:01:46 PM PDT 24	Jul 24 08:05:52 PM PDT 24	2489779900 ps
T81	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1696340109			Jul 24 07:59:45 PM PDT 24	Jul 24 08:22:13 PM PDT 24	10419375408 ps
T111	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4213964143			Jul 24 08:03:58 PM PDT 24	Jul 24 08:08:16 PM PDT 24	2941469744 ps
T21	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2159332301			Jul 24 07:58:46 PM PDT 24	Jul 24 08:53:13 PM PDT 24	20405759613 ps
T49	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.686206169			Jul 24 08:14:27 PM PDT 24	Jul 24 09:19:06 PM PDT 24	15191193640 ps
T419	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3762980016			Jul 24 08:23:07 PM PDT 24	Jul 24 08:34:36 PM PDT 24	4826210140 ps
T371	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3142093859			Jul 24 08:27:53 PM PDT 24	Jul 24 08:36:12 PM PDT 24	4514211146 ps
T214	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.4127005156			Jul 24 08:02:18 PM PDT 24	Jul 24 08:15:55 PM PDT 24	4015425080 ps
T420	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1925296442			Jul 24 08:08:05 PM PDT 24	Jul 24 08:13:02 PM PDT 24	2916728839 ps
T244	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3100898574			Jul 24 08:02:16 PM PDT 24	Jul 24 08:13:11 PM PDT 24	6534525076 ps
T268	/workspace/coverage/default/0.chip_sw_example_manufacturer.1204155146			Jul 24 07:56:34 PM PDT 24	Jul 24 07:59:58 PM PDT 24	2734961656 ps
T269	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.666323160			Jul 24 08:08:36 PM PDT 24	Jul 24 08:18:18 PM PDT 24	4729443202 ps
T10	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3868111001			Jul 24 08:11:38 PM PDT 24	Jul 24 08:17:17 PM PDT 24	3496676268 ps
T171	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1282658249			Jul 24 08:07:26 PM PDT 24	Jul 24 08:24:55 PM PDT 24	10231755416 ps
T45	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2423694639			Jul 24 08:04:08 PM PDT 24	Jul 24 09:13:13 PM PDT 24	14113225401 ps
T270	/workspace/coverage/default/1.chip_sw_aes_idle.1287567811			Jul 24 08:05:27 PM PDT 24	Jul 24 08:10:20 PM PDT 24	3104932000 ps
T140	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.94761004			Jul 24 08:05:18 PM PDT 24	Jul 24 08:10:04 PM PDT 24	3125317567 ps
T271	/workspace/coverage/default/0.rom_keymgr_functest.4216589585			Jul 24 08:05:35 PM PDT 24	Jul 24 08:13:49 PM PDT 24	4155635798 ps
T272	/workspace/coverage/default/2.chip_sw_hmac_multistream.2884919319			Jul 24 08:17:12 PM PDT 24	Jul 24 08:38:02 PM PDT 24	6980651190 ps
T338	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1079944911			Jul 24 08:22:00 PM PDT 24	Jul 24 08:32:32 PM PDT 24	3303464716 ps
T342	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3127512286			Jul 24 08:19:30 PM PDT 24	Jul 24 08:23:20 PM PDT 24	3036004504 ps
T976	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2662559788			Jul 24 07:58:27 PM PDT 24	Jul 24 08:14:59 PM PDT 24	5696974674 ps
T259	/workspace/coverage/default/1.chip_plic_all_irqs_0.1837814405			Jul 24 08:05:22 PM PDT 24	Jul 24 08:25:53 PM PDT 24	6090649312 ps
T977	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.452890069			Jul 24 08:18:04 PM PDT 24	Jul 24 08:24:39 PM PDT 24	4388759038 ps
T170	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2509221894			Jul 24 07:57:58 PM PDT 24	Jul 24 09:37:35 PM PDT 24	51901053975 ps
T116	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2398394920			Jul 24 07:59:35 PM PDT 24	Jul 24 10:05:35 PM PDT 24	41297016328 ps
T216	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1108415473			Jul 24 07:57:07 PM PDT 24	Jul 24 08:17:19 PM PDT 24	8249131664 ps
T121	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.526667729			Jul 24 08:00:16 PM PDT 24	Jul 24 08:10:52 PM PDT 24	4563510488 ps
T978	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3727734993			Jul 24 08:12:00 PM PDT 24	Jul 24 08:20:14 PM PDT 24	5030383892 ps
T979	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3649385481			Jul 24 08:24:02 PM PDT 24	Jul 24 08:33:36 PM PDT 24	6358720760 ps
T543	/workspace/coverage/default/34.chip_sw_all_escalation_resets.2739352834			Jul 24 08:24:53 PM PDT 24	Jul 24 08:36:44 PM PDT 24	4912264520 ps
T242	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.84317090			Jul 24 07:55:46 PM PDT 24	Jul 24 08:06:26 PM PDT 24	5567388904 ps
T46	/workspace/coverage/default/1.rom_e2e_shutdown_output.2508064514			Jul 24 08:13:45 PM PDT 24	Jul 24 09:07:54 PM PDT 24	27906725060 ps
T122	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2347123376			Jul 24 08:06:45 PM PDT 24	Jul 24 08:18:23 PM PDT 24	4908428120 ps
T368	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3312738956			Jul 24 08:21:29 PM PDT 24	Jul 24 08:30:13 PM PDT 24	4650633144 ps
T330	/workspace/coverage/default/1.chip_sival_flash_info_access.3465296363			Jul 24 07:59:49 PM PDT 24	Jul 24 08:05:02 PM PDT 24	2524488620 ps
T69	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1143284401			Jul 24 07:57:00 PM PDT 24	Jul 24 10:48:50 PM PDT 24	58427588958 ps
T773	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1771181416			Jul 24 08:21:39 PM PDT 24	Jul 24 08:28:13 PM PDT 24	3143566850 ps
T221	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.103272201			Jul 24 08:17:48 PM PDT 24	Jul 24 08:47:20 PM PDT 24	10285795118 ps
T13	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1392611691			Jul 24 07:56:53 PM PDT 24	Jul 24 08:05:51 PM PDT 24	4384579326 ps
T62	/workspace/coverage/default/3.chip_tap_straps_rma.2587651133			Jul 24 08:21:46 PM PDT 24	Jul 24 08:28:29 PM PDT 24	3945770610 ps
T243	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.755310410			Jul 24 08:05:42 PM PDT 24	Jul 24 08:17:33 PM PDT 24	5117861290 ps
T774	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2783908761			Jul 24 08:25:16 PM PDT 24	Jul 24 08:33:44 PM PDT 24	4208592476 ps
T126	/workspace/coverage/default/1.chip_sw_edn_boot_mode.851481034			Jul 24 08:05:00 PM PDT 24	Jul 24 08:12:57 PM PDT 24	3474128118 ps
T123	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3578621202			Jul 24 07:59:34 PM PDT 24	Jul 24 08:08:54 PM PDT 24	3950931354 ps
T980	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1865763901			Jul 24 08:07:31 PM PDT 24	Jul 24 08:10:26 PM PDT 24	2790171218 ps
T147	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1601046544			Jul 24 08:19:10 PM PDT 24	Jul 24 08:30:38 PM PDT 24	4323018980 ps
T411	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3605707618			Jul 24 08:08:00 PM PDT 24	Jul 24 09:14:48 PM PDT 24	15582426880 ps
T981	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1776116334			Jul 24 08:05:29 PM PDT 24	Jul 24 08:09:12 PM PDT 24	2426070700 ps
T211	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.988462401			Jul 24 08:11:28 PM PDT 24	Jul 24 08:24:34 PM PDT 24	4952652704 ps
T128	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.158455113			Jul 24 08:22:30 PM PDT 24	Jul 24 08:36:19 PM PDT 24	9085837580 ps
T372	/workspace/coverage/default/99.chip_sw_all_escalation_resets.813005435			Jul 24 08:28:41 PM PDT 24	Jul 24 08:41:20 PM PDT 24	5614759076 ps
T220	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1227317950			Jul 24 08:12:31 PM PDT 24	Jul 24 08:26:07 PM PDT 24	4535577470 ps
T804	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2899527011			Jul 24 08:05:42 PM PDT 24	Jul 24 08:29:44 PM PDT 24	8071764340 ps
T339	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1785333676			Jul 24 07:56:03 PM PDT 24	Jul 24 08:04:58 PM PDT 24	4252207056 ps
T210	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3983184180			Jul 24 08:16:21 PM PDT 24	Jul 24 08:46:03 PM PDT 24	7146810780 ps
T260	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3183716210			Jul 24 08:02:08 PM PDT 24	Jul 24 08:33:15 PM PDT 24	10830012012 ps
T39	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2268559080			Jul 24 08:02:15 PM PDT 24	Jul 24 08:09:46 PM PDT 24	5723091100 ps
T744	/workspace/coverage/default/2.chip_sw_edn_kat.350702710			Jul 24 08:19:44 PM PDT 24	Jul 24 08:30:31 PM PDT 24	3734118920 ps
T982	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2387018495			Jul 24 08:02:28 PM PDT 24	Jul 24 08:05:31 PM PDT 24	2642457130 ps
T222	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.339733298			Jul 24 07:59:08 PM PDT 24	Jul 24 08:23:44 PM PDT 24	7897267850 ps
T77	/workspace/coverage/default/2.chip_jtag_mem_access.2506985848			Jul 24 08:09:16 PM PDT 24	Jul 24 08:32:55 PM PDT 24	13990831544 ps
T778	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3502677262			Jul 24 08:27:15 PM PDT 24	Jul 24 08:32:24 PM PDT 24	3714869624 ps
T129	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2113644007			Jul 24 08:19:03 PM PDT 24	Jul 24 08:34:37 PM PDT 24	6631509392 ps
T772	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1480070167			Jul 24 08:27:38 PM PDT 24	Jul 24 08:33:49 PM PDT 24	3526593526 ps
T983	/workspace/coverage/default/2.chip_sw_example_concurrency.323521602			Jul 24 08:11:03 PM PDT 24	Jul 24 08:14:16 PM PDT 24	2307813224 ps
T148	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.560573346			Jul 24 08:04:30 PM PDT 24	Jul 24 09:05:36 PM PDT 24	17641910450 ps
T984	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.15543573			Jul 24 08:19:46 PM PDT 24	Jul 24 08:29:10 PM PDT 24	3604019008 ps
T776	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4093950166			Jul 24 08:25:56 PM PDT 24	Jul 24 08:33:36 PM PDT 24	3542482130 ps
T17	/workspace/coverage/default/2.chip_sw_gpio.874023866			Jul 24 08:10:28 PM PDT 24	Jul 24 08:19:59 PM PDT 24	4476471480 ps
T397	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3663176028			Jul 24 08:11:36 PM PDT 24	Jul 24 08:16:29 PM PDT 24	2916097952 ps
T985	/workspace/coverage/default/2.chip_sw_aes_idle.3356903694			Jul 24 08:14:45 PM PDT 24	Jul 24 08:19:35 PM PDT 24	3018318256 ps
T986	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2715118792			Jul 24 08:06:54 PM PDT 24	Jul 24 08:12:59 PM PDT 24	4589405718 ps
T149	/workspace/coverage/default/1.chip_sw_otbn_smoketest.980854392			Jul 24 08:09:44 PM PDT 24	Jul 24 08:35:50 PM PDT 24	7142626930 ps
T223	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1595822212			Jul 24 08:06:20 PM PDT 24	Jul 24 08:23:44 PM PDT 24	6256595952 ps
T360	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1136810164			Jul 24 08:29:08 PM PDT 24	Jul 24 08:38:00 PM PDT 24	5211266260 ps
T19	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3280327025			Jul 24 08:01:30 PM PDT 24	Jul 24 08:09:26 PM PDT 24	6273575940 ps
T987	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.199828149			Jul 24 08:15:48 PM PDT 24	Jul 24 08:25:41 PM PDT 24	5616529790 ps
T449	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.531119228			Jul 24 08:18:58 PM PDT 24	Jul 24 08:24:18 PM PDT 24	3825493588 ps
T323	/workspace/coverage/default/2.chip_plic_all_irqs_0.960458433			Jul 24 08:16:25 PM PDT 24	Jul 24 08:34:13 PM PDT 24	6298471608 ps
T233	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3718012515			Jul 24 07:58:55 PM PDT 24	Jul 24 08:33:36 PM PDT 24	19565275331 ps
T264	/workspace/coverage/default/83.chip_sw_all_escalation_resets.461087381			Jul 24 08:29:02 PM PDT 24	Jul 24 08:37:49 PM PDT 24	4411187664 ps
T988	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2396501686			Jul 24 08:01:08 PM PDT 24	Jul 24 08:18:00 PM PDT 24	10366814804 ps
T832	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.963475574			Jul 24 08:03:18 PM PDT 24	Jul 24 08:11:44 PM PDT 24	3945590168 ps
T172	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1112553760			Jul 24 08:01:44 PM PDT 24	Jul 24 08:43:29 PM PDT 24	32723370052 ps
T358	/workspace/coverage/default/2.chip_sw_pattgen_ios.2621932296			Jul 24 08:12:19 PM PDT 24	Jul 24 08:16:56 PM PDT 24	2704939448 ps
T82	/workspace/coverage/default/51.chip_sw_all_escalation_resets.999585859			Jul 24 08:26:20 PM PDT 24	Jul 24 08:33:51 PM PDT 24	5128368600 ps
T93	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3547905741			Jul 24 08:28:56 PM PDT 24	Jul 24 08:35:41 PM PDT 24	3163451320 ps
T94	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4030098514			Jul 24 08:24:57 PM PDT 24	Jul 24 08:35:14 PM PDT 24	3376897662 ps
T95	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2390479070			Jul 24 07:56:39 PM PDT 24	Jul 24 08:29:37 PM PDT 24	7660252750 ps
T96	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.618726314			Jul 24 08:15:15 PM PDT 24	Jul 24 08:20:20 PM PDT 24	2827240100 ps
T97	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3415111547			Jul 24 08:08:34 PM PDT 24	Jul 24 08:24:08 PM PDT 24	7701655842 ps
T98	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2316869727			Jul 24 08:13:02 PM PDT 24	Jul 24 08:54:06 PM PDT 24	21568306362 ps
T99	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1600952500			Jul 24 08:28:07 PM PDT 24	Jul 24 08:35:00 PM PDT 24	3719544908 ps
T100	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1779440544			Jul 24 08:32:00 PM PDT 24	Jul 24 08:39:29 PM PDT 24	3986872022 ps
T101	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.621088456			Jul 24 08:08:58 PM PDT 24	Jul 24 08:12:59 PM PDT 24	3130231636 ps
T989	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.61661746			Jul 24 08:15:24 PM PDT 24	Jul 24 08:20:15 PM PDT 24	2722177720 ps
T179	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.495956573			Jul 24 08:17:38 PM PDT 24	Jul 24 08:21:55 PM PDT 24	2800540284 ps
T306	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2650968600			Jul 24 08:14:36 PM PDT 24	Jul 24 08:37:28 PM PDT 24	8413485560 ps
T137	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2335295393			Jul 24 08:00:40 PM PDT 24	Jul 24 08:16:03 PM PDT 24	6025242648 ps
T234	/workspace/coverage/default/0.chip_sw_flash_init.3863957158			Jul 24 07:58:29 PM PDT 24	Jul 24 08:39:34 PM PDT 24	17062283000 ps
T177	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1555764447			Jul 24 08:16:13 PM PDT 24	Jul 24 08:29:49 PM PDT 24	4891090730 ps
T70	/workspace/coverage/default/1.chip_tap_straps_rma.1915888816			Jul 24 08:11:18 PM PDT 24	Jul 24 08:17:48 PM PDT 24	4274887300 ps
T27	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.587919109			Jul 24 08:10:48 PM PDT 24	Jul 24 08:17:50 PM PDT 24	4261673814 ps
T20	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3952278655			Jul 24 08:16:28 PM PDT 24	Jul 24 08:39:12 PM PDT 24	20084365068 ps
T307	/workspace/coverage/default/10.chip_sw_all_escalation_resets.879925685			Jul 24 08:22:33 PM PDT 24	Jul 24 08:33:25 PM PDT 24	4634605384 ps
T308	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3249075885			Jul 24 08:16:08 PM PDT 24	Jul 24 08:29:33 PM PDT 24	5692799538 ps
T22	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2985044122			Jul 24 08:01:54 PM PDT 24	Jul 24 08:24:36 PM PDT 24	22934937000 ps
T261	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.715646093			Jul 24 08:02:12 PM PDT 24	Jul 24 08:38:32 PM PDT 24	10817389982 ps
T326	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.712179844			Jul 24 08:23:34 PM PDT 24	Jul 24 08:34:16 PM PDT 24	4567776224 ps
T11	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3210718330			Jul 24 07:56:32 PM PDT 24	Jul 24 08:00:55 PM PDT 24	2372297518 ps
T235	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3463116617			Jul 24 08:11:37 PM PDT 24	Jul 24 09:38:51 PM PDT 24	48659168288 ps
T245	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1916004209			Jul 24 08:13:18 PM PDT 24	Jul 24 08:22:57 PM PDT 24	5664149604 ps
T856	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3073973071			Jul 24 08:22:22 PM PDT 24	Jul 24 08:31:24 PM PDT 24	6039934578 ps
T990	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.354133881			Jul 24 08:02:10 PM PDT 24	Jul 24 08:36:57 PM PDT 24	24313258783 ps
T314	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1513026659			Jul 24 08:13:31 PM PDT 24	Jul 24 11:44:36 PM PDT 24	255620682774 ps
T112	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3164986818			Jul 24 08:19:13 PM PDT 24	Jul 24 08:27:06 PM PDT 24	4421777942 ps
T237	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1698428675			Jul 24 08:11:51 PM PDT 24	Jul 24 09:40:45 PM PDT 24	50894440326 ps
T47	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3982599873			Jul 24 08:08:15 PM PDT 24	Jul 24 09:19:36 PM PDT 24	17206957705 ps
T391	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3484793749			Jul 24 08:13:17 PM PDT 24	Jul 24 09:23:24 PM PDT 24	15074481339 ps
T246	/workspace/coverage/default/32.chip_sw_all_escalation_resets.287231474			Jul 24 08:23:59 PM PDT 24	Jul 24 08:32:46 PM PDT 24	6350307952 ps
T315	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3701937987			Jul 24 08:11:07 PM PDT 24	Jul 24 08:19:33 PM PDT 24	5328294755 ps
T439	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1283026899			Jul 24 07:56:20 PM PDT 24	Jul 24 08:00:55 PM PDT 24	3556638620 ps
T156	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.371479080			Jul 24 07:58:40 PM PDT 24	Jul 24 08:06:24 PM PDT 24	4779498160 ps
T150	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3346866463			Jul 24 08:13:55 PM PDT 24	Jul 24 09:10:34 PM PDT 24	17726066180 ps
T316	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.4234368512			Jul 24 08:10:13 PM PDT 24	Jul 24 08:36:53 PM PDT 24	12628192616 ps
T238	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3879728469			Jul 24 08:07:27 PM PDT 24	Jul 24 08:41:06 PM PDT 24	17536232937 ps
T991	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1715521362			Jul 24 07:58:53 PM PDT 24	Jul 24 08:03:10 PM PDT 24	3426973210 ps
T777	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.643675587			Jul 24 07:57:43 PM PDT 24	Jul 24 08:05:49 PM PDT 24	3350615324 ps
T199	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3771707923			Jul 24 08:05:32 PM PDT 24	Jul 24 11:58:55 PM PDT 24	78582998860 ps
T872	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.382516024			Jul 24 08:27:17 PM PDT 24	Jul 24 08:33:12 PM PDT 24	3830157020 ps
T224	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.242958528			Jul 24 08:17:44 PM PDT 24	Jul 24 08:43:50 PM PDT 24	9238478680 ps
T141	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.31864251			Jul 24 07:57:47 PM PDT 24	Jul 24 08:07:13 PM PDT 24	7582572811 ps
T250	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1915973241			Jul 24 08:26:03 PM PDT 24	Jul 24 08:31:55 PM PDT 24	4009213156 ps
T298	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1693863733			Jul 24 08:32:57 PM PDT 24	Jul 24 08:39:29 PM PDT 24	4016161416 ps
T24	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3386142984			Jul 24 07:57:15 PM PDT 24	Jul 24 10:16:14 PM PDT 24	32074123726 ps
T204	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3164371053			Jul 24 08:06:00 PM PDT 24	Jul 24 08:10:48 PM PDT 24	2663816858 ps
T157	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2937690133			Jul 24 08:31:26 PM PDT 24	Jul 24 08:40:43 PM PDT 24	5090501992 ps
T299	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1621578224			Jul 24 08:10:29 PM PDT 24	Jul 24 08:21:43 PM PDT 24	4211074936 ps
T300	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3239676277			Jul 24 08:04:24 PM PDT 24	Jul 24 08:13:54 PM PDT 24	4999314432 ps
T301	/workspace/coverage/default/4.chip_sw_uart_tx_rx.2676894788			Jul 24 08:21:02 PM PDT 24	Jul 24 08:30:56 PM PDT 24	4018352420 ps
T178	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1517352386			Jul 24 08:04:51 PM PDT 24	Jul 24 08:15:12 PM PDT 24	5297709560 ps
T302	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4201900803			Jul 24 07:57:20 PM PDT 24	Jul 24 08:50:45 PM PDT 24	39933922052 ps
T781	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1894616218			Jul 24 08:28:22 PM PDT 24	Jul 24 08:34:53 PM PDT 24	4009070034 ps
T992	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3375583289			Jul 24 08:22:21 PM PDT 24	Jul 24 09:15:19 PM PDT 24	15423527868 ps
T993	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3775141645			Jul 24 08:02:27 PM PDT 24	Jul 24 08:20:50 PM PDT 24	5445283198 ps
T381	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3459371190			Jul 24 08:23:21 PM PDT 24	Jul 24 08:33:17 PM PDT 24	4903151096 ps
T159	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2847843550			Jul 24 08:25:58 PM PDT 24	Jul 24 08:35:43 PM PDT 24	5724423468 ps
T384	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.441013199			Jul 24 08:28:35 PM PDT 24	Jul 24 08:32:51 PM PDT 24	2829832432 ps
T385	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172548265			Jul 24 08:27:32 PM PDT 24	Jul 24 08:33:57 PM PDT 24	4106060406 ps
T386	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1833842345			Jul 24 08:23:53 PM PDT 24	Jul 24 08:30:09 PM PDT 24	3150007000 ps
T387	/workspace/coverage/default/0.chip_sw_aes_enc.348365780			Jul 24 07:57:24 PM PDT 24	Jul 24 08:02:02 PM PDT 24	2894039400 ps
T14	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3559868279			Jul 24 08:11:16 PM PDT 24	Jul 24 08:23:01 PM PDT 24	4940067682 ps
T388	/workspace/coverage/default/1.chip_sw_example_manufacturer.3783468093			Jul 24 08:06:02 PM PDT 24	Jul 24 08:10:16 PM PDT 24	2396641884 ps
T389	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3807992351			Jul 24 08:17:00 PM PDT 24	Jul 24 08:25:20 PM PDT 24	3486509912 ps
T390	/workspace/coverage/default/1.chip_sw_csrng_kat_test.908267689			Jul 24 08:08:42 PM PDT 24	Jul 24 08:12:51 PM PDT 24	3345439900 ps
T83	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3325257653			Jul 24 08:27:57 PM PDT 24	Jul 24 08:35:12 PM PDT 24	3672358830 ps
T808	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3867619854			Jul 24 08:22:06 PM PDT 24	Jul 24 08:31:28 PM PDT 24	5472020200 ps
T840	/workspace/coverage/default/89.chip_sw_all_escalation_resets.3722456814			Jul 24 08:28:34 PM PDT 24	Jul 24 08:40:34 PM PDT 24	5493675806 ps
T173	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3236896877			Jul 24 07:58:39 PM PDT 24	Jul 24 08:17:01 PM PDT 24	12785428765 ps
T742	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1226979594			Jul 24 08:20:25 PM PDT 24	Jul 24 09:36:50 PM PDT 24	23598526450 ps
T349	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.750203685			Jul 24 08:17:12 PM PDT 24	Jul 24 08:24:39 PM PDT 24	3418684900 ps
T343	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.494077035			Jul 24 07:56:39 PM PDT 24	Jul 24 08:34:52 PM PDT 24	13852585130 ps
T994	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3989435644			Jul 24 08:12:53 PM PDT 24	Jul 24 08:17:11 PM PDT 24	2173573480 ps
T455	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1699352437			Jul 24 07:57:59 PM PDT 24	Jul 24 09:02:02 PM PDT 24	19207866128 ps
T23	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1902638438			Jul 24 08:14:01 PM PDT 24	Jul 24 08:38:55 PM PDT 24	24784069770 ps
T354	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.83347043			Jul 24 08:02:26 PM PDT 24	Jul 24 08:14:33 PM PDT 24	4547217208 ps
T995	/workspace/coverage/default/0.chip_tap_straps_dev.985180783			Jul 24 08:02:08 PM PDT 24	Jul 24 08:05:13 PM PDT 24	2586420278 ps
T226	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1157434555			Jul 24 08:05:57 PM PDT 24	Jul 24 08:15:33 PM PDT 24	6008217576 ps
T452	/workspace/coverage/default/1.chip_sw_kmac_entropy.3155503706			Jul 24 08:00:44 PM PDT 24	Jul 24 08:05:18 PM PDT 24	2600374100 ps
T779	/workspace/coverage/default/52.chip_sw_all_escalation_resets.3513247178			Jul 24 08:27:21 PM PDT 24	Jul 24 08:36:09 PM PDT 24	5626968796 ps
T407	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1871777503			Jul 24 08:16:19 PM PDT 24	Jul 24 08:33:25 PM PDT 24	11453457912 ps
T324	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3364288581			Jul 24 07:56:13 PM PDT 24	Jul 24 08:21:19 PM PDT 24	11371615043 ps
T996	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3122226683			Jul 24 08:05:11 PM PDT 24	Jul 24 08:17:49 PM PDT 24	7272949160 ps
T997	/workspace/coverage/default/0.rom_e2e_static_critical.1370807452			Jul 24 08:02:36 PM PDT 24	Jul 24 09:09:11 PM PDT 24	17291904440 ps
T998	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2955772301			Jul 24 08:08:11 PM PDT 24	Jul 24 08:15:46 PM PDT 24	4988754076 ps
T453	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1052969425			Jul 24 08:03:51 PM PDT 24	Jul 24 08:24:28 PM PDT 24	6471897444 ps
T278	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1003169956			Jul 24 07:59:59 PM PDT 24	Jul 24 08:11:13 PM PDT 24	8442643830 ps
T999	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4228121356			Jul 24 07:57:44 PM PDT 24	Jul 24 08:06:46 PM PDT 24	8302700118 ps
T266	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1805796817			Jul 24 08:33:19 PM PDT 24	Jul 24 08:44:17 PM PDT 24	5957291864 ps
T327	/workspace/coverage/default/2.chip_plic_all_irqs_20.1550643016			Jul 24 08:15:38 PM PDT 24	Jul 24 08:29:07 PM PDT 24	4793274328 ps
T770	/workspace/coverage/default/94.chip_sw_all_escalation_resets.1389198632			Jul 24 08:29:04 PM PDT 24	Jul 24 08:36:35 PM PDT 24	4831403156 ps
T289	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3128936908			Jul 24 08:22:01 PM PDT 24	Jul 24 08:30:54 PM PDT 24	4925251000 ps
T784	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3466924998			Jul 24 08:26:47 PM PDT 24	Jul 24 08:36:43 PM PDT 24	4279426662 ps
T225	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2740169661			Jul 24 08:15:16 PM PDT 24	Jul 24 08:40:12 PM PDT 24	10052042524 ps
T892	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348025677			Jul 24 08:28:02 PM PDT 24	Jul 24 08:33:01 PM PDT 24	3943226830 ps
T102	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3839878399			Jul 24 08:06:19 PM PDT 24	Jul 24 08:10:22 PM PDT 24	3103083656 ps
T257	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3624673507			Jul 24 08:02:19 PM PDT 24	Jul 24 08:06:36 PM PDT 24	3347669880 ps
T1000	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3228191033			Jul 24 07:59:26 PM PDT 24	Jul 24 08:18:06 PM PDT 24	7778284740 ps
T851	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2347388145			Jul 24 08:25:11 PM PDT 24	Jul 24 08:36:08 PM PDT 24	5228028600 ps
T845	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896129246			Jul 24 08:28:40 PM PDT 24	Jul 24 08:36:34 PM PDT 24	4220441368 ps
T230	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3349632179			Jul 24 08:01:11 PM PDT 24	Jul 24 08:08:48 PM PDT 24	5093477815 ps