Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3274	1			T398	5		T506	2		T552	1
all_values[1]	3348	1			T398	2		T506	2		T552	2
all_values[2]	3270	1			T398	9		T506	2		T552	2
all_values[3]	3322	1			T398	4		T506	2		T547	12
all_values[4]	3352	1			T398	3		T506	5		T552	1
all_values[5]	3346	1			T398	3		T506	5		T552	1
all_values[6]	3286	1			T398	2		T506	4		T547	12
all_values[7]	3289	1			T398	4		T506	1		T552	1
all_values[8]	3314	1			T398	3		T506	2		T547	12
all_values[9]	3262	1			T398	4		T506	3		T552	1
all_values[10]	3191	1			T398	3		T506	3		T547	13
all_values[11]	3309	1			T398	9		T506	1		T552	3
all_values[12]	3276	1			T398	7		T506	1		T552	2
all_values[13]	3159	1			T398	2		T506	2		T547	14
all_values[14]	3335	1			T398	5		T506	3		T552	1
all_values[15]	3268	1			T398	5		T506	1		T552	1
all_values[16]	3252	1			T398	4		T506	1		T552	1
all_values[17]	3324	1			T398	1		T506	3		T552	1
all_values[18]	3256	1			T398	9		T506	2		T552	1
all_values[19]	3231	1			T398	6		T506	2		T552	2
all_values[20]	3269	1			T398	7		T506	2		T552	1
all_values[21]	3210	1			T398	4		T506	2		T552	1
all_values[22]	3306	1			T398	3		T506	2		T547	6
all_values[23]	3303	1			T398	3		T506	1		T547	13
all_values[24]	3315	1			T398	5		T506	3		T547	8
all_values[25]	3321	1			T398	4		T506	1		T547	14
all_values[26]	3327	1			T398	6		T506	2		T552	4
all_values[27]	3236	1			T398	12		T552	1		T547	10
all_values[28]	3262	1			T398	2		T506	1		T547	18
all_values[29]	3245	1			T398	4		T506	5		T552	1
all_values[30]	3251	1			T398	4		T506	3		T552	1
all_values[31]	3167	1			T398	11		T506	2		T552	2
all_values[32]	3254	1			T398	5		T547	18		T553	1
all_values[33]	3356	1			T398	3		T506	3		T552	2
all_values[34]	3188	1			T398	8		T552	1		T547	23
all_values[35]	3250	1			T398	1		T506	4		T547	15
all_values[36]	3236	1			T398	4		T506	3		T552	1
all_values[37]	3229	1			T398	7		T506	2		T547	8
all_values[38]	3257	1			T398	5		T506	4		T547	15
all_values[39]	3262	1			T398	4		T506	5		T552	1
all_values[40]	3245	1			T398	4		T506	2		T547	13
all_values[41]	3298	1			T398	4		T506	5		T552	1
all_values[42]	3239	1			T552	1		T547	15		T553	1
all_values[43]	3375	1			T398	8		T552	2		T547	17
all_values[44]	3324	1			T398	4		T506	2		T552	1
all_values[45]	3257	1			T398	5		T506	3		T552	1
all_values[46]	3238	1			T398	6		T506	2		T547	15
all_values[47]	3219	1			T398	6		T506	3		T547	9
all_values[48]	3215	1			T398	1		T506	2		T552	1
all_values[49]	3326	1			T398	3		T506	1		T547	11
all_values[50]	3265	1			T398	4		T506	2		T552	1
all_values[51]	3275	1			T398	4		T506	1		T547	18
all_values[52]	3310	1			T398	9		T506	1		T547	17
all_values[53]	3329	1			T398	3		T506	1		T547	24
all_values[54]	3298	1			T398	3		T506	4		T552	1
all_values[55]	3379	1			T398	3		T506	6		T552	1
all_values[56]	3187	1			T398	9		T506	3		T547	18
all_values[57]	3363	1			T398	5		T506	3		T552	1
all_values[58]	3238	1			T398	7		T506	3		T552	1
all_values[59]	3158	1			T398	3		T506	2		T552	1
all_values[60]	3126	1			T398	7		T506	1		T547	9
all_values[61]	3264	1			T398	6		T552	2		T547	8
all_values[62]	3287	1			T398	3		T506	1		T547	19
all_values[63]	3246	1			T398	8		T547	16		T440	3