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 LINE       17945
 EXPRESSION (addr_hit[197] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T4
1	0	1	Covered	T329,T259,T330
1	1	0	Covered	T572,T648,T708
1	1	1	Covered	T329,T259,T330

 LINE       17998
 EXPRESSION (addr_hit[198] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T4
1	0	1	Covered	T395,T143,T144
1	1	0	Covered	T566,T567,T563
1	1	1	Covered	T1,T9,T4

 LINE       18001
 EXPRESSION (addr_hit[199] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T4
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       18002
 EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T4
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T572,T618,T645
1	1	1	Covered	T1,T4,T5

 LINE       18005
 EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T4
1	0	1	Covered	T106,T255,T395
1	1	0	Covered	T566,T572,T565
1	1	1	Covered	T106,T255,T256

 LINE       18008
 EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T9,T4
1	0	1	Covered	T395,T143,T144
1	1	0	Covered	T568,T566,T619
1	1	1	Covered	T50,T51,T249