Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3655973	1			T79	7621		T80	114		T81	122
values[2]	713888	1			T79	939		T80	44		T81	31
values[3]	97866	1			T79	65		T80	3		T81	2
values[4]	52624	1			T79	30		T131	1		T446	45
values[5]	36280	1			T79	19		T446	14		T430	107
values[6]	26914	1			T79	23		T446	3		T430	69
values[7]	22210	1			T79	12		T430	74		T663	12
values[8]	18717	1			T79	4		T430	84		T663	12
values[9]	16658	1			T79	8		T430	89		T663	12
values[10]	15288	1			T79	5		T430	106		T663	12
values[11]	14085	1			T79	2		T430	87		T663	12
values[12]	13118	1			T430	79		T663	12		T404	4
values[13]	12389	1			T430	63		T663	12		T404	3
values[14]	12045	1			T430	32		T663	13		T404	6
values[15]	11634	1			T430	31		T663	12		T404	7
values[16]	10837	1			T430	15		T663	12		T404	22
values[17]	10413	1			T430	14		T663	12		T404	12
values[18]	10024	1			T430	10		T663	12		T404	5
values[19]	9920	1			T430	7		T663	13		T404	12
values[20]	9671	1			T430	12		T663	12		T404	7
values[21]	9444	1			T430	14		T663	12		T404	6
values[22]	9080	1			T430	7		T663	12		T404	7
values[23]	8787	1			T430	3		T663	13		T404	10
values[24]	8486	1			T430	4		T663	12		T404	8
values[25]	8162	1			T430	6		T663	12		T404	8
values[26]	7992	1			T430	15		T663	12		T404	10
values[27]	7810	1			T430	13		T663	12		T404	12
values[28]	7381	1			T430	12		T663	12		T404	5
values[29]	6813	1			T430	12		T663	12		T404	2
values[30]	6181	1			T430	10		T663	12		T404	2
values[31]	5720	1			T430	6		T663	12		T404	3
values[32]	5378	1			T430	6		T663	12		T404	2
values[33]	5092	1			T430	4		T663	12		T404	3
values[34]	4648	1			T430	3		T663	12		T404	3
values[35]	4372	1			T430	5		T663	12		T404	4
values[36]	4104	1			T430	7		T663	13		T404	5
values[37]	4000	1			T430	5		T663	12		T404	3
values[38]	3836	1			T430	3		T663	13		T404	5
values[39]	3615	1			T430	3		T663	12		T404	8
values[40]	3481	1			T430	4		T663	12		T404	3
values[41]	3316	1			T430	3		T663	12		T404	4
values[42]	3282	1			T430	2		T663	12		T404	8
values[43]	3220	1			T430	8		T663	12		T404	14
values[44]	3117	1			T430	5		T663	12		T404	12
values[45]	2942	1			T430	2		T663	12		T404	15
values[46]	2907	1			T430	4		T663	12		T404	8
values[47]	2866	1			T430	2		T663	12		T404	6
values[48]	2801	1			T430	2		T663	12		T404	3
values[49]	2704	1			T430	5		T663	12		T404	8
values[50]	2672	1			T430	3		T663	12		T404	4
values[51]	2699	1			T430	6		T663	12		T404	5
values[52]	2648	1			T430	4		T663	12		T404	2
values[53]	2640	1			T430	5		T663	13		T404	3
values[54]	2567	1			T430	5		T663	12		T404	4
values[55]	2536	1			T430	4		T663	12		T404	5
values[56]	2486	1			T430	5		T663	12		T404	5
values[57]	2415	1			T430	6		T663	12		T404	4
values[58]	2397	1			T430	4		T663	12		T404	6
values[59]	2434	1			T430	5		T663	12		T404	3
values[60]	2418	1			T430	2		T663	13		T404	8
values[61]	2682	1			T430	3		T663	12		T404	10
values[62]	4036	1			T430	9		T663	12		T404	16
values[63]	10682	1			T430	68		T663	13		T404	49
values[64]	220775	1			T430	183		T663	2143		T404	116

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4647795	1			T79	8545		T80	98		T81	163
values[2]	776373	1			T79	990		T80	24		T81	32
values[3]	80173	1			T79	102		T80	3		T81	4
values[4]	13821	1			T79	3		T131	5		T258	1
values[5]	5236	1			T446	2		T526	3		T430	23
values[6]	3258	1			T526	1		T430	31		T663	4
values[7]	2454	1			T430	11		T663	3		T527	8
values[8]	2159	1			T430	16		T663	1		T527	9
values[9]	1951	1			T430	17		T663	1		T527	6
values[10]	1681	1			T430	13		T663	1		T527	2
values[11]	1547	1			T430	11		T663	1		T527	1
values[12]	1496	1			T430	9		T663	1		T527	4
values[13]	1350	1			T430	7		T663	1		T527	1
values[14]	1285	1			T430	3		T663	1		T527	1
values[15]	1340	1			T430	6		T663	1		T527	2
values[16]	1163	1			T430	4		T663	1		T527	1
values[17]	1173	1			T430	5		T663	1		T527	4
values[18]	994	1			T430	7		T663	1		T527	3
values[19]	927	1			T430	3		T663	1		T527	9
values[20]	922	1			T430	2		T663	1		T527	3
values[21]	846	1			T430	3		T663	1		T527	1
values[22]	851	1			T430	9		T663	1		T527	1
values[23]	837	1			T430	3		T663	1		T527	2
values[24]	828	1			T430	3		T663	1		T527	3
values[25]	814	1			T430	4		T663	1		T527	5
values[26]	743	1			T430	3		T663	1		T527	6
values[27]	723	1			T430	2		T663	1		T527	12
values[28]	683	1			T430	3		T663	1		T527	11
values[29]	649	1			T430	5		T663	1		T527	5
values[30]	673	1			T430	3		T663	1		T527	1
values[31]	688	1			T430	7		T663	1		T527	1
values[32]	608	1			T430	6		T663	1		T527	2
values[33]	583	1			T430	6		T663	1		T527	9
values[34]	540	1			T430	5		T663	1		T527	5
values[35]	549	1			T430	3		T663	1		T527	2
values[36]	530	1			T430	1		T663	1		T527	3
values[37]	496	1			T430	2		T663	1		T527	1
values[38]	513	1			T430	3		T663	1		T527	1
values[39]	488	1			T430	1		T663	1		T527	1
values[40]	504	1			T430	1		T663	1		T527	1
values[41]	491	1			T430	1		T663	1		T527	1
values[42]	465	1			T430	1		T663	1		T527	2
values[43]	481	1			T430	1		T663	1		T527	3
values[44]	482	1			T430	2		T663	1		T527	6
values[45]	422	1			T430	1		T663	1		T527	10
values[46]	438	1			T430	1		T663	1		T527	4
values[47]	454	1			T430	5		T663	1		T527	1
values[48]	443	1			T430	3		T663	1		T527	1
values[49]	430	1			T430	3		T663	1		T527	10
values[50]	374	1			T430	1		T663	1		T527	4
values[51]	426	1			T430	1		T663	1		T527	1
values[52]	424	1			T430	2		T663	1		T527	1
values[53]	389	1			T430	3		T663	1		T527	1
values[54]	391	1			T430	3		T663	1		T527	2
values[55]	377	1			T430	3		T663	2		T527	1
values[56]	370	1			T430	1		T663	1		T527	1
values[57]	403	1			T430	1		T663	1		T527	1
values[58]	390	1			T430	1		T663	1		T527	1
values[59]	371	1			T430	1		T663	1		T527	1
values[60]	377	1			T430	2		T663	1		T527	7
values[61]	433	1			T430	3		T663	1		T527	6
values[62]	651	1			T430	11		T663	1		T527	6
values[63]	2358	1			T430	46		T663	1		T527	13
values[64]	28410	1			T430	54		T663	225		T527	16

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	586963	1			T79	3176		T80	1		T81	1
values[2]	2585324	1			T79	2422		T80	13		T81	95
values[3]	1140234	1			T79	2551		T80	147		T81	65
values[4]	134460	1			T79	250		T80	3		T81	2
values[5]	69751	1			T79	119		T446	268		T430	377
values[6]	45611	1			T79	71		T446	163		T430	238
values[7]	33436	1			T79	29		T446	87		T430	180
values[8]	26895	1			T79	6		T446	79		T430	119
values[9]	22840	1			T79	19		T446	53		T430	95
values[10]	19914	1			T79	15		T446	58		T430	76
values[11]	17830	1			T79	8		T446	59		T430	67
values[12]	16741	1			T79	1		T446	29		T430	60
values[13]	16014	1			T446	27		T430	41		T663	12
values[14]	15015	1			T446	28		T430	27		T663	12
values[15]	14134	1			T446	11		T430	20		T663	12
values[16]	13692	1			T446	12		T430	30		T663	12
values[17]	13034	1			T446	21		T430	33		T663	12
values[18]	12599	1			T446	15		T430	21		T663	12
values[19]	11678	1			T446	16		T430	15		T663	12
values[20]	11345	1			T446	22		T430	21		T663	12
values[21]	10901	1			T446	10		T430	21		T663	12
values[22]	10241	1			T446	9		T430	29		T663	12
values[23]	9877	1			T446	9		T430	28		T663	12
values[24]	9540	1			T446	12		T430	14		T663	12
values[25]	9286	1			T446	11		T430	18		T663	12
values[26]	8870	1			T446	17		T430	11		T663	12
values[27]	8260	1			T446	9		T430	10		T663	12
values[28]	7736	1			T446	16		T430	7		T663	12
values[29]	7252	1			T446	10		T430	20		T663	12
values[30]	7214	1			T446	5		T430	16		T663	12
values[31]	6752	1			T446	2		T430	9		T663	12
values[32]	6313	1			T446	2		T430	9		T663	12
values[33]	5823	1			T446	2		T430	18		T663	12
values[34]	5212	1			T446	1		T430	8		T663	12
values[35]	4808	1			T446	2		T430	9		T663	12
values[36]	4600	1			T430	3		T663	13		T404	9
values[37]	4090	1			T430	10		T663	12		T404	6
values[38]	3963	1			T430	13		T663	12		T404	8
values[39]	3947	1			T430	5		T663	13		T404	4
values[40]	3634	1			T430	5		T663	12		T404	2
values[41]	3544	1			T430	3		T663	12		T404	2
values[42]	3468	1			T430	5		T663	12		T404	2
values[43]	3430	1			T430	7		T663	12		T404	3
values[44]	3435	1			T430	11		T663	13		T404	10
values[45]	3342	1			T430	10		T663	12		T404	5
values[46]	3287	1			T430	6		T663	12		T404	6
values[47]	3189	1			T430	7		T663	12		T404	6
values[48]	3107	1			T430	7		T663	12		T404	7
values[49]	3047	1			T430	10		T663	12		T404	3
values[50]	3053	1			T430	8		T663	12		T404	3
values[51]	3052	1			T430	2		T663	12		T404	3
values[52]	2958	1			T430	2		T663	12		T404	2
values[53]	2902	1			T430	3		T663	12		T404	4
values[54]	2877	1			T430	9		T663	12		T404	4
values[55]	2779	1			T430	3		T663	12		T404	2
values[56]	2704	1			T430	3		T663	12		T404	3
values[57]	2708	1			T430	2		T663	12		T404	4
values[58]	2681	1			T430	2		T663	12		T404	3
values[59]	2671	1			T430	3		T663	12		T404	6
values[60]	2710	1			T430	2		T663	14		T404	6
values[61]	2816	1			T430	2		T663	12		T404	9
values[62]	3780	1			T430	8		T663	13		T404	17
values[63]	9343	1			T430	62		T663	12		T404	63
values[64]	216400	1			T430	199		T663	2301		T404	183