Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2032332	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

39774474

1

T1

50560

T2

348

T3

536494

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29127122	1			T1	47039		T2	175		T3	357000
values[0x0]	11147643	1			T1	3521		T2	173		T3	179494
values[0x1]	1532041	1			T1	13111		T2	3		T3	6536

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	643466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41163340

1

T1

63671

T2

351

T3

543030

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19715458	1			T1	31836		T2	176		T3	271515
valid_sources[0x01]	19716107	1			T1	31835		T2	175		T3	271515
valid_sources[0x02]	37870	1			T150	1		T151	156		T369	3046
valid_sources[0x03]	38842	1			T84	1		T210	1		T151	173
valid_sources[0x04]	39188	1			T84	1		T211	1		T151	184
valid_sources[0x05]	38432	1			T210	3		T150	1		T151	228
valid_sources[0x06]	38330	1			T211	1		T151	174		T369	3109
valid_sources[0x07]	37912	1			T84	1		T150	1		T151	171
valid_sources[0x08]	38355	1			T150	1		T151	177		T369	3135
valid_sources[0x09]	38649	1			T84	1		T210	1		T151	170
valid_sources[0x0a]	37773	1			T84	1		T211	1		T151	166
valid_sources[0x0b]	40011	1			T210	2		T151	182		T369	2977
valid_sources[0x0c]	37479	1			T211	3		T150	1		T151	156
valid_sources[0x0d]	38669	1			T84	1		T150	1		T151	179
valid_sources[0x0e]	37718	1			T211	3		T150	1		T151	169
valid_sources[0x0f]	38275	1			T211	2		T151	170		T369	2860
valid_sources[0x10]	38581	1			T210	4		T150	1		T151	168
valid_sources[0x11]	38479	1			T84	1		T210	4		T150	1
valid_sources[0x12]	38242	1			T53	39		T211	1		T151	175
valid_sources[0x13]	37855	1			T210	1		T211	2		T151	169
valid_sources[0x14]	38815	1			T84	1		T210	1		T211	1
valid_sources[0x15]	37578	1			T150	1		T151	167		T369	3187
valid_sources[0x16]	38149	1			T151	204		T369	2788		T530	14
valid_sources[0x17]	37215	1			T211	2		T151	184		T369	2686
valid_sources[0x18]	39130	1			T84	1		T151	167		T369	2978
valid_sources[0x19]	38444	1			T84	3		T210	1		T211	2
valid_sources[0x1a]	37347	1			T84	1		T211	2		T151	162
valid_sources[0x1b]	38521	1			T211	1		T150	1		T151	180
valid_sources[0x1c]	38454	1			T84	1		T210	1		T151	174
valid_sources[0x1d]	37617	1			T210	1		T151	175		T369	2969
valid_sources[0x1e]	38055	1			T84	1		T150	1		T151	173
valid_sources[0x1f]	38823	1			T211	1		T150	1		T151	157
valid_sources[0x20]	38332	1			T210	4		T150	1		T151	176

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28420262

1

T1

47039

T2

175

T3

357000

values[0x0]

all_enables

biggest_size

11088795

1

T1

3521

T2

173

T3

179494

values[0x1]

all_enables

biggest_size

265417

1

T8

26

T53

22

T84

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2745523	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

434030

1

T79

1219

T80

21

T81

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1076710	1			T79	2859		T80	51		T81	49
values[0x0]	1025636	1			T79	2894		T80	65		T81	46
values[0x1]	1077207	1			T79	2975		T80	45		T81	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2124933	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1054620

1

T79

2894

T80

41

T81

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49616	1			T79	210		T80	4		T81	3
valid_sources[0x01]	50225	1			T79	171		T80	4		T131	48
valid_sources[0x02]	49979	1			T79	79		T80	2		T81	2
valid_sources[0x03]	49479	1			T79	158		T81	1		T131	47
valid_sources[0x04]	48808	1			T79	116		T81	5		T131	56
valid_sources[0x05]	49931	1			T79	116		T80	1		T81	2
valid_sources[0x06]	50377	1			T79	136		T131	41		T258	2
valid_sources[0x07]	49863	1			T79	102		T81	5		T131	27
valid_sources[0x08]	49383	1			T79	226		T80	7		T81	7
valid_sources[0x09]	50100	1			T79	107		T80	1		T131	26
valid_sources[0x0a]	49874	1			T79	114		T80	2		T131	58
valid_sources[0x0b]	50177	1			T79	258		T80	4		T131	41
valid_sources[0x0c]	49916	1			T79	254		T81	1		T131	42
valid_sources[0x0d]	50453	1			T79	116		T81	2		T131	63
valid_sources[0x0e]	50204	1			T79	158		T81	1		T131	34
valid_sources[0x0f]	49886	1			T79	101		T80	1		T81	4
valid_sources[0x10]	49518	1			T79	187		T80	3		T81	2
valid_sources[0x11]	51204	1			T79	155		T80	1		T131	36
valid_sources[0x12]	48632	1			T79	111		T80	8		T81	2
valid_sources[0x13]	51013	1			T79	208		T80	4		T81	1
valid_sources[0x14]	49813	1			T79	28		T80	2		T131	52
valid_sources[0x15]	48705	1			T79	76		T80	2		T131	30
valid_sources[0x16]	49719	1			T79	157		T80	5		T81	1
valid_sources[0x17]	49945	1			T79	100		T80	1		T81	1
valid_sources[0x18]	49167	1			T79	79		T80	10		T131	28
valid_sources[0x19]	49562	1			T79	63		T80	2		T81	4
valid_sources[0x1a]	50125	1			T79	158		T80	7		T81	5
valid_sources[0x1b]	49459	1			T79	169		T80	1		T81	1
valid_sources[0x1c]	48853	1			T79	133		T80	1		T81	1
valid_sources[0x1d]	50131	1			T79	183		T80	2		T81	3
valid_sources[0x1e]	50977	1			T79	63		T131	36		T258	2
valid_sources[0x1f]	49639	1			T79	133		T81	3		T131	51
valid_sources[0x20]	49222	1			T79	188		T80	6		T81	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45541

1

T79

102

T131

39

T258

6

values[0x0]

all_enables

biggest_size

343066

1

T79

955

T80

21

T81

21

values[0x1]

all_enables

biggest_size

45423

1

T79

162

T81

3

T131

41

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2922787	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

476569

1

T79

1352

T80

24

T81

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1165108	1			T79	3238		T80	42		T81	77
values[0x0]	1069853	1			T79	2972		T80	41		T81	65
values[0x1]	1164395	1			T79	3430		T80	42		T81	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2242768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1156588

1

T79

3341

T80

47

T81

66

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53668	1			T79	262		T81	5		T131	36
valid_sources[0x01]	52600	1			T79	166		T80	17		T81	3
valid_sources[0x02]	53671	1			T79	121		T81	4		T131	40
valid_sources[0x03]	54002	1			T79	154		T81	2		T131	43
valid_sources[0x04]	52217	1			T79	138		T81	5		T131	31
valid_sources[0x05]	53001	1			T79	104		T131	39		T258	1
valid_sources[0x06]	53344	1			T79	98		T80	1		T81	3
valid_sources[0x07]	53445	1			T79	121		T81	3		T131	41
valid_sources[0x08]	53200	1			T79	158		T81	2		T131	41
valid_sources[0x09]	52615	1			T79	167		T81	9		T131	54
valid_sources[0x0a]	54052	1			T79	98		T80	1		T81	4
valid_sources[0x0b]	54008	1			T79	286		T80	2		T81	1
valid_sources[0x0c]	53157	1			T79	255		T81	3		T131	57
valid_sources[0x0d]	54043	1			T79	89		T81	2		T131	32
valid_sources[0x0e]	53470	1			T79	181		T80	1		T131	51
valid_sources[0x0f]	52814	1			T79	188		T131	54		T258	2
valid_sources[0x10]	52987	1			T79	172		T81	8		T131	44
valid_sources[0x11]	53496	1			T79	150		T80	5		T81	5
valid_sources[0x12]	52760	1			T79	131		T80	5		T81	3
valid_sources[0x13]	53347	1			T79	220		T81	7		T131	40
valid_sources[0x14]	53079	1			T79	60		T81	3		T131	45
valid_sources[0x15]	53441	1			T79	55		T81	1		T131	37
valid_sources[0x16]	53266	1			T79	153		T80	2		T81	4
valid_sources[0x17]	52897	1			T79	164		T80	3		T81	1
valid_sources[0x18]	52965	1			T79	93		T81	4		T131	50
valid_sources[0x19]	52477	1			T79	79		T81	2		T131	50
valid_sources[0x1a]	52953	1			T79	161		T80	2		T81	5
valid_sources[0x1b]	52454	1			T79	183		T81	5		T131	35
valid_sources[0x1c]	52609	1			T79	162		T81	3		T131	48
valid_sources[0x1d]	52116	1			T79	136		T81	2		T131	32
valid_sources[0x1e]	53806	1			T79	129		T81	1		T131	31
valid_sources[0x1f]	52976	1			T79	154		T81	2		T131	42
valid_sources[0x20]	53378	1			T79	114		T80	11		T131	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50293

1

T79

136

T80

4

T81

5

values[0x0]

all_enables

biggest_size

376122

1

T79

1075

T80

19

T81

22

values[0x1]

all_enables

biggest_size

50154

1

T79

141

T80

1

T81

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2768088	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

438666

1

T79

1226

T80

22

T81

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1086809	1			T79	2929		T80	58		T81	61
values[0x0]	1033983	1			T79	2826		T80	55		T81	50
values[0x1]	1085962	1			T79	2912		T80	51		T81	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2143330	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1063424

1

T79

2962

T80

55

T81

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50477	1			T79	189		T80	2		T131	34
valid_sources[0x01]	50327	1			T79	148		T80	1		T131	27
valid_sources[0x02]	50980	1			T79	113		T80	4		T81	4
valid_sources[0x03]	50214	1			T79	133		T80	1		T81	2
valid_sources[0x04]	50182	1			T79	94		T80	4		T131	13
valid_sources[0x05]	50130	1			T79	145		T81	3		T131	35
valid_sources[0x06]	51068	1			T79	114		T80	1		T81	7
valid_sources[0x07]	50316	1			T79	130		T80	2		T131	20
valid_sources[0x08]	49996	1			T79	214		T80	3		T131	35
valid_sources[0x09]	49976	1			T79	100		T80	5		T131	38
valid_sources[0x0a]	50741	1			T79	129		T131	28		T258	2
valid_sources[0x0b]	50491	1			T79	187		T80	1		T81	2
valid_sources[0x0c]	50363	1			T79	222		T80	7		T131	52
valid_sources[0x0d]	50651	1			T79	117		T80	2		T81	6
valid_sources[0x0e]	49848	1			T79	160		T80	4		T81	10
valid_sources[0x0f]	50280	1			T79	147		T80	3		T81	2
valid_sources[0x10]	49105	1			T79	156		T80	4		T81	1
valid_sources[0x11]	50126	1			T79	158		T80	6		T131	38
valid_sources[0x12]	49775	1			T79	134		T80	4		T131	18
valid_sources[0x13]	50630	1			T79	170		T80	1		T81	1
valid_sources[0x14]	50152	1			T79	64		T80	4		T81	5
valid_sources[0x15]	49861	1			T79	63		T80	1		T81	5
valid_sources[0x16]	50943	1			T79	155		T80	4		T81	7
valid_sources[0x17]	50065	1			T79	121		T81	7		T131	17
valid_sources[0x18]	50080	1			T79	90		T80	3		T81	11
valid_sources[0x19]	49884	1			T79	92		T80	2		T81	1
valid_sources[0x1a]	50146	1			T79	138		T80	2		T81	4
valid_sources[0x1b]	49416	1			T79	181		T80	3		T81	6
valid_sources[0x1c]	50144	1			T79	173		T80	2		T131	34
valid_sources[0x1d]	50633	1			T79	150		T80	2		T131	18
valid_sources[0x1e]	50512	1			T79	105		T131	46		T446	7
valid_sources[0x1f]	49153	1			T79	115		T80	2		T81	7
valid_sources[0x20]	50416	1			T79	152		T80	4		T131	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46068

1

T79

103

T80

3

T81

2

values[0x0]

all_enables

biggest_size

346479

1

T79

997

T80

16

T81

16

values[0x1]

all_enables

biggest_size

46119

1

T79

126

T80

3

T81

1