Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544852857	63536296	0	0
DepthKnown_A	544852857	544744750	0	0
RvalidKnown_A	544852857	544744750	0	0
WreadyKnown_A	544852857	544744750	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	63536296	0	0
T1	593158	52952	0	0
T2	81339	3461	0	0
T3	838609	118370	0	0
T4	72219	10600	0	0
T5	215711	21856	0	0
T6	165677	16933	0	0
T7	370375	29330	0	0
T8	113704	0	0	0
T33	166487	17567	0	0
T92	147769	22820	0	0
T119	0	9318	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544852857	49532154	0	0
DepthKnown_A	544852857	544744750	0	0
RvalidKnown_A	544852857	544744750	0	0
WreadyKnown_A	544852857	544744750	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	49532154	0	0
T1	593158	48976	0	0
T2	81339	1868	0	0
T3	838609	116230	0	0
T4	72219	6910	0	0
T5	215711	17876	0	0
T6	165677	13140	0	0
T7	370375	21798	0	0
T8	113704	0	0	0
T33	166487	13937	0	0
T92	147769	18772	0	0
T119	0	6942	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544852857	46350985	0	0
DepthKnown_A	544852857	544744750	0	0
RvalidKnown_A	544852857	544744750	0	0
WreadyKnown_A	544852857	544744750	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	46350985	0	0
T1	593158	63876	0	0
T2	81339	459	0	0
T3	838609	543769	0	0
T4	72219	3968	0	0
T5	215711	20512	0	0
T6	165677	9266	0	0
T7	370375	17032	0	0
T8	113704	39	0	0
T33	166487	10731	0	0
T92	147769	11610	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544852857	39456233	0	0
DepthKnown_A	544852857	544744750	0	0
RvalidKnown_A	544852857	544744750	0	0
WreadyKnown_A	544852857	544744750	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	39456233	0	0
T1	593158	63671	0	0
T2	81339	351	0	0
T3	838609	543030	0	0
T4	72219	3845	0	0
T5	215711	20307	0	0
T6	165677	8766	0	0
T7	370375	16524	0	0
T8	113704	172	0	0
T33	166487	10490	0	0
T92	147769	11494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544852857	544744750	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621702531	94629	0	0
DepthKnown_A	621702531	621578766	0	0
RvalidKnown_A	621702531	621578766	0	0
WreadyKnown_A	621702531	621578766	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	94629	0	0
T1	593158	53	0	0
T2	81339	8	0	0
T3	838609	104	0	0
T4	72219	13	0	0
T5	215711	53	0	0
T6	165677	59	0	0
T7	370375	68	0	0
T8	113704	0	0	0
T33	166487	27	0	0
T92	147769	13	0	0
T119	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621702531	96939	0	0
DepthKnown_A	621702531	621578766	0	0
RvalidKnown_A	621702531	621578766	0	0
WreadyKnown_A	621702531	621578766	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	96939	0	0
T1	593158	53	0	0
T2	81339	8	0	0
T3	838609	104	0	0
T4	72219	13	0	0
T5	215711	53	0	0
T6	165677	59	0	0
T7	370375	68	0	0
T8	113704	0	0	0
T33	166487	27	0	0
T92	147769	13	0	0
T119	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621702531	54594	0	0
DepthKnown_A	621702531	621578766	0	0
RvalidKnown_A	621702531	621578766	0	0
WreadyKnown_A	621702531	621578766	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	54594	0	0
T1	593158	52	0	0
T2	81339	8	0	0
T3	838609	42	0	0
T4	72219	12	0	0
T5	215711	52	0	0
T6	165677	56	0	0
T7	370375	64	0	0
T8	113704	0	0	0
T33	166487	25	0	0
T92	147769	12	0	0
T119	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621702531	54593	0	0
DepthKnown_A	621702531	621578766	0	0
RvalidKnown_A	621702531	621578766	0	0
WreadyKnown_A	621702531	621578766	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	54593	0	0
T1	593158	52	0	0
T2	81339	8	0	0
T3	838609	42	0	0
T4	72219	12	0	0
T5	215711	52	0	0
T6	165677	56	0	0
T7	370375	64	0	0
T8	113704	0	0	0
T33	166487	25	0	0
T92	147769	12	0	0
T119	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621702531	40035	0	0
DepthKnown_A	621702531	621578766	0	0
RvalidKnown_A	621702531	621578766	0	0
WreadyKnown_A	621702531	621578766	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	40035	0	0
T1	593158	1	0	0
T2	81339	0	0	0
T3	838609	62	0	0
T4	72219	1	0	0
T5	215711	1	0	0
T6	165677	3	0	0
T7	370375	4	0	0
T8	113704	0	0	0
T33	166487	2	0	0
T92	147769	1	0	0
T119	0	1	0	0
T202	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621702531	42346	0	0
DepthKnown_A	621702531	621578766	0	0
RvalidKnown_A	621702531	621578766	0	0
WreadyKnown_A	621702531	621578766	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	42346	0	0
T1	593158	1	0	0
T2	81339	0	0	0
T3	838609	62	0	0
T4	72219	1	0	0
T5	215711	1	0	0
T6	165677	3	0	0
T7	370375	4	0	0
T8	113704	0	0	0
T33	166487	2	0	0
T92	147769	1	0	0
T119	0	1	0	0
T202	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621702531	621578766	0	0
T1	593158	593103	0	0
T2	81339	81277	0	0
T3	838609	838603	0	0
T4	72219	72161	0	0
T5	215711	215660	0	0
T6	165677	165622	0	0
T7	370375	370025	0	0
T8	113704	113692	0	0
T33	166487	166367	0	0
T92	147769	147714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0