Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T203,T49	Yes	T5,T203,T49	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T203,T49	Yes	T5,T203,T49	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T8,*T82,*T83	Yes	T8,T82,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T8,T53,T84	Yes	T8,T53,T84	INPUT
tl_i.a_valid	Yes	Yes	T5,T203,T49	Yes	T5,T203,T49	INPUT
tl_o.a_ready	Yes	Yes	T5,T203,T49	Yes	T5,T203,T49	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T203,T49	Yes	T5,T203,T49	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T203,T49	Yes	T5,T203,T49	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T203,T49	Yes	T5,T203,T49	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T262,*T263,*T210	Yes	T262,T263,T210	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T203,*T49	Yes	T5,T203,T49	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T203,T49	Yes	T5,T203,T49	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T227,T363,T85	Yes	T227,T363,T85	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T227,T363,T85	Yes	T227,T363,T85	OUTPUT
cio_rx_i	Yes	Yes	T5,T7,T33	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T5,T49,T153	Yes	T5,T49,T153	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T203,T153	Yes	T5,T203,T153	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T203,T153	Yes	T5,T203,T153	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T203,T153	Yes	T5,T203,T153	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T203,T153	Yes	T5,T203,T153	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T203,T153	Yes	T5,T203,T153	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T203,T49,T50	Yes	T203,T49,T50	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T203,T49,T50	Yes	T203,T49,T50	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T8,*T82,*T83	Yes	T8,T82,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T8,T53,T84	Yes	T8,T53,T84	INPUT
tl_i.a_valid	Yes	Yes	T203,T49,T50	Yes	T203,T49,T50	INPUT
tl_o.a_ready	Yes	Yes	T203,T49,T50	Yes	T203,T49,T50	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T203,T49,T50	Yes	T203,T49,T50	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T203,T49,T50	Yes	T203,T49,T50	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T203,T49,T50	Yes	T203,T49,T50	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T262,*T263,*T210	Yes	T262,T263,T210	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T203,*T49,*T50	Yes	T203,T49,T50	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T203,T49,T50	Yes	T203,T49,T50	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T227,T85,T163	Yes	T227,T85,T163	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T227,T85,T163	Yes	T227,T85,T163	OUTPUT
cio_rx_i	Yes	Yes	T7,T33,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T203,T224,T307	Yes	T203,T224,T307	OUTPUT
intr_tx_empty_o	Yes	Yes	T203,T224,T307	Yes	T203,T224,T307	OUTPUT
intr_rx_watermark_o	Yes	Yes	T203,T224,T307	Yes	T203,T224,T307	OUTPUT
intr_tx_done_o	Yes	Yes	T203,T224,T307	Yes	T203,T224,T307	OUTPUT
intr_rx_overflow_o	Yes	Yes	T203,T224,T307	Yes	T203,T224,T307	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T8,*T82,*T83	Yes	T8,T82,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T8,T53,T84	Yes	T8,T53,T84	INPUT
tl_i.a_valid	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	INPUT
tl_o.a_ready	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T210,*T150,*T79	Yes	T210,T150,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T203,*T91	Yes	T5,T203,T91	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T712,T163	Yes	T85,T712,T163	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T712,T163	Yes	T85,T712,T163	OUTPUT
cio_rx_i	Yes	Yes	T5,T91,T35	Yes	T5,T91,T10	INPUT
cio_tx_o	Yes	Yes	T5,T91,T300	Yes	T5,T91,T300	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T203,T91	Yes	T5,T203,T91	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T8,*T82,*T83	Yes	T8,T82,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T8,T53,T84	Yes	T8,T53,T84	INPUT
tl_i.a_valid	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	INPUT
tl_o.a_ready	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T210,*T150,*T79	Yes	T210,T150,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T131,T258	Yes	T79,T131,T258	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T203,*T153,*T154	Yes	T203,T153,T154	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T363,T85,T713	Yes	T363,T85,T713	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T363,T85,T713	Yes	T363,T85,T713	OUTPUT
cio_rx_i	Yes	Yes	T153,T154,T125	Yes	T153,T154,T125	INPUT
cio_tx_o	Yes	Yes	T153,T154,T125	Yes	T153,T154,T125	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
intr_tx_empty_o	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
intr_rx_watermark_o	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
intr_tx_done_o	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
intr_rx_overflow_o	Yes	Yes	T203,T153,T154	Yes	T203,T153,T154	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T8,*T82,*T83	Yes	T8,T82,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T8,T53,T84	Yes	T8,T53,T84	INPUT
tl_i.a_valid	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	INPUT
tl_o.a_ready	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
tl_o.d_error	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T210,*T150,*T79	Yes	T210,T150,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T16,*T203	Yes	T1,T16,T203	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T345,T163	Yes	T85,T345,T163	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T88,T89	Yes	T85,T88,T89	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T345,T163	Yes	T85,T345,T163	OUTPUT
cio_rx_i	Yes	Yes	T1,T16,T17	Yes	T1,T16,T17	INPUT
cio_tx_o	Yes	Yes	T1,T16,T17	Yes	T1,T16,T17	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
intr_tx_empty_o	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
intr_rx_watermark_o	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
intr_tx_done_o	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
intr_rx_overflow_o	Yes	Yes	T1,T16,T203	Yes	T1,T16,T203	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T322,T320	Yes	T203,T322,T320	OUTPUT

*Tests covering at least one bit in the range