Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T79,T131,T258	Yes	T79,T131,T258	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T227,T228,T82	Yes	T227,T228,T82	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T227,T228,T82	Yes	T227,T228,T82	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T8,T53,T84	Yes	T8,T53,T84	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T8,T84,T210	Yes	T8,T84,T210	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T8,T84,T210	Yes	T8,T84,T210	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T34,T70,T71	Yes	T34,T70,T71	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T2,T8,T74	Yes	T2,T8,T74	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T7,T8	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T2,T8,T74	Yes	T2,T8,T74	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T2,T8,T74	Yes	T2,T8,T74	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T2,T7,T8	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T2,T8,T74	Yes	T2,T8,T74	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T8,T74	Yes	T2,T8,T74	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T2,T8,T74	Yes	T2,T8,T74	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T2,*T8,*T74	Yes	T2,T8,T74	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T2,T8,T74	Yes	T2,T8,T74	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T79,T81,T131	Yes	T79,T80,T131	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T79,T81,T131	Yes	T79,T80,T131	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T79,T80,T131	Yes	T79,T80,T81	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T79,*T80,*T131	Yes	T79,T80,T131	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T82,T83,T262	Yes	T82,T83,T262	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T82,T83,T262	Yes	T82,T83,T262	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T82,T83,T262	Yes	T82,T83,T262	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T82,T83,T262	Yes	T82,T83,T262	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T82,T83,T262	Yes	T82,T83,T262	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T82,*T83,*T262	Yes	T82,T83,T262	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T82,T83,T262	Yes	T82,T83,T262	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T7,T8,T33	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T82,T83,T262	Yes	T82,T83,T262	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T82,T83,T262	Yes	T82,T83,T262	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T7,T8,T33	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T262	Yes	T82,T83,T262	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T7,T8,T33	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T82,T83,T262	Yes	T82,T83,T262	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T2,T8,T174	Yes	T2,T8,T174	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T8,T174,T49	Yes	T8,T174,T49	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T272,T386,T387	Yes	T272,T386,T387	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T272,T386,T387	Yes	T272,T386,T387	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T272,T386,T387	Yes	T272,T386,T387	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	T79,*T81,*T131	Yes	T79,T81,T131	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T272,T386,T387	Yes	T272,T386,T387	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T272,T386,T387	Yes	T272,T386,T387	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T272,T386,T387	Yes	T272,T386,T387	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T79,T81,T131	Yes	T54,T55,T56	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T272,T386,T387	Yes	T272,T386,T387	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T272,*T387,*T388	Yes	T272,T386,T387	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T272,T386,T387	Yes	T272,T386,T387	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T8,*T82,*T83	Yes	T8,T82,T83	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T8,T53,T84	Yes	T8,T53,T84	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T70,T227,T228	Yes	T70,T227,T228	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T8,*T83,*T262	Yes	T8,T82,T83	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T14,T205,T209	Yes	T14,T205,T209	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T159,T160,T13	Yes	T159,T160,T13	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T159,T160,T13	Yes	T159,T160,T13	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T131	Yes	T79,T80,T131	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T79,T131,T258	Yes	T79,T81,T131	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T159,*T160,*T390	Yes	T159,T160,T390	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T163,T255,T159	Yes	T163,T255,T159	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T35,*T159,*T160	Yes	T35,T159,T160	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T35,T159,T160	Yes	T35,T159,T160	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T203,T18,T19	Yes	T203,T18,T19	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T210,*T150,*T79	Yes	T210,T150,T79	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T79,T131,T258	Yes	T79,T131,T258	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	INPUT
tl_usbdev_i.d_error	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T210,*T150,*T79	Yes	T210,T150,T79	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T203,*T18,*T377	Yes	T203,T18,T377	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T203,T18,T377	Yes	T203,T18,T377	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T7,T8,T33	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T7,T33,T34	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T150,T79,T80	Yes	T150,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T150,T79,T81	Yes	T150,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T150,T79,T80	Yes	T150,T79,T80	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T7,T8,T33	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T202,T364,T299	Yes	T202,T364,T299	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	INPUT
tl_hmac_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	INPUT
tl_hmac_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T202,*T49,*T50	Yes	T202,T49,T50	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T202,T49,T50	Yes	T202,T49,T50	INPUT
tl_kmac_o.d_ready	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T229,T239,T441	Yes	T229,T239,T441	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T229,T239,T441	Yes	T229,T239,T441	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T53,*T150,*T79	Yes	T53,T150,T79	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T229,T441,T442	Yes	T229,T441,T442	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	INPUT
tl_kmac_i.d_error	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	INPUT
tl_kmac_i.d_sink	Yes	Yes	T79,T81,T131	Yes	T79,T80,T81	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T53,*T150,*T79	Yes	T53,T150,T79	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T158,*T229,*T230	Yes	T158,T229,T230	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	INPUT
tl_aes_o.d_ready	Yes	Yes	T3,T7,T8	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T119,T120,T290	Yes	T119,T120,T290	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T119,T120,T290	Yes	T119,T120,T290	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T3,T119,T120	Yes	T3,T119,T120	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T119,T120,T290	Yes	T119,T120,T290	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T3,T119,T120	Yes	T3,T119,T120	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T53,*T79,*T80	Yes	T53,T79,T80	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T3,T119,T120	Yes	T3,T119,T120	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T3,T119,T120	Yes	T3,T119,T120	INPUT
tl_aes_i.d_error	Yes	Yes	T79,T80,T131	Yes	T79,T80,T81	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T3,T119,T120	Yes	T3,T119,T120	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T119,T120	Yes	T3,T119,T120	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T3,T119,T120	Yes	T3,T119,T120	INPUT
tl_aes_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T53,*T79,*T80	Yes	T53,T79,T80	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T131	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T3,*T119,*T120	Yes	T3,T119,T120	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T3,T119,T120	Yes	T3,T119,T120	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T3,T92,T128	Yes	T3,T92,T128	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T92,T7	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T3,T92,T7	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T3,*T92,*T128	Yes	T3,T92,T128	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T3,T128,T639	Yes	T3,T128,T639	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T53,*T150,*T79	Yes	T53,T150,T79	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T3,T128,T639	Yes	T3,T128,T639	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T7,T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T3,T7,T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T53,*T150,*T79	Yes	T53,T150,T79	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T3,*T128,*T639	Yes	T3,T128,T639	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T7,T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T3,T7,T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T3,*T128,*T642	Yes	T3,T128,T642	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T3,T7,T8	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	INPUT
tl_edn1_i.d_error	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T128,T129	Yes	T3,T128,T642	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T3,T128,T129	Yes	T3,T128,T642	INPUT
tl_edn1_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T150,*T79,*T81	Yes	T150,T79,T80	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T131	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T3,*T128,*T642	Yes	T3,T128,T642	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T3,T128,T642	Yes	T3,T128,T642	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T131	Yes	T79,T80,T131	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T79,T131,T258	Yes	T79,T131,T258	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T79,*T131,*T258	Yes	T79,T80,T131	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T5,*T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_otbn_o.d_ready	Yes	Yes	T3,T7,T8	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T8,*T53,*T84	Yes	T8,T53,T84	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	INPUT
tl_otbn_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	INPUT
tl_otbn_i.d_sink	Yes	Yes	T79,T80,T131	Yes	T79,T80,T81	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T8,*T53,*T84	Yes	T8,T53,T84	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T3,*T8,*T49	Yes	T3,T8,T49	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T3,T8,T49	Yes	T3,T8,T49	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T33,T158,T49	Yes	T33,T158,T49	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T33,T158,T49	Yes	T33,T158,T49	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T33,T158,T49	Yes	T33,T158,T49	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T158,T50,T229	Yes	T158,T50,T229	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T33,T158,T49	Yes	T33,T158,T49	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T150,*T79,*T80	Yes	T150,T79,T80	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T33,T158,T49	Yes	T33,T158,T49	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T33,T158,T49	Yes	T33,T158,T49	INPUT
tl_keymgr_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T158,T229,T230	Yes	T158,T229,T230	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T158,T49	Yes	T33,T158,T49	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T33,T158,T49	Yes	T33,T158,T49	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T150,*T79,*T81	Yes	T150,T79,T80	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T158,*T49,*T50	Yes	T33,T158,T49	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T33,T158,T49	Yes	T33,T158,T49	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T262,*T263,*T264	Yes	T262,T263,T264	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T3,T6,T202	Yes	T3,T6,T202	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T3,T6,T202	Yes	T3,T6,T202	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T131	Yes	T262,T263,T264	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T7,T8,T33	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T49,T121,T50	Yes	T49,T121,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T49,T121,T50	Yes	T49,T121,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T49,T121,T50	Yes	T49,T121,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T49,T121,T50	Yes	T49,T121,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T49,T121,T50	Yes	T49,T121,T50	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T411,*T427,*T79	Yes	T411,T427,T79	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T49,T121,T50	Yes	T49,T121,T50	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T49,T121,T50	Yes	T49,T121,T50	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T79,T80,T131	Yes	T79,T80,T131	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T189,T305,T306	Yes	T189,T305,T306	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T121,T46,T47	Yes	T49,T121,T50	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T121,T46,T47	Yes	T49,T121,T50	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T79,T80,T131	Yes	T79,T81,T131	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T131	Yes	T411,T427,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T79,T81,T131	Yes	T79,T81,T131	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T121,*T122,*T189	Yes	T121,T98,T122	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T49,T121,T50	Yes	T49,T121,T50	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T7,T8,T33	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range