Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1028	1028	0	0
OutputsKnown_A	138164409	137485075	0	0
gen_no_flops.OutputDelay_A	138164409	137485075	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138164409	137485075	0	0
T1	143273	142734	0	0
T2	20362	19888	0	0
T3	323064	323017	0	0
T4	18280	17700	0	0
T5	52604	52142	0	0
T6	60667	60218	0	0
T7	96248	93668	0	0
T8	274248	273243	0	0
T33	41380	40720	0	0
T92	36562	35834	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138164409	137485075	0	0
T1	143273	142734	0	0
T2	20362	19888	0	0
T3	323064	323017	0	0
T4	18280	17700	0	0
T5	52604	52142	0	0
T6	60667	60218	0	0
T7	96248	93668	0	0
T8	274248	273243	0	0
T33	41380	40720	0	0
T92	36562	35834	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1028	1028	0	0
OutputsKnown_A	138164409	137485075	0	0
gen_no_flops.OutputDelay_A	138164409	137485075	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T33	1	1	0	0
T92	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138164409	137485075	0	0
T1	143273	142734	0	0
T2	20362	19888	0	0
T3	323064	323017	0	0
T4	18280	17700	0	0
T5	52604	52142	0	0
T6	60667	60218	0	0
T7	96248	93668	0	0
T8	274248	273243	0	0
T33	41380	40720	0	0
T92	36562	35834	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138164409	137485075	0	0
T1	143273	142734	0	0
T2	20362	19888	0	0
T3	323064	323017	0	0
T4	18280	17700	0	0
T5	52604	52142	0	0
T6	60667	60218	0	0
T7	96248	93668	0	0
T8	274248	273243	0	0
T33	41380	40720	0	0
T92	36562	35834	0	0