Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3799756	1			T71	61		T72	1998		T73	727
values[2]	774915	1			T71	19		T72	620		T73	204
values[3]	117564	1			T71	23		T72	37		T73	5
values[4]	63451	1			T71	1		T539	24		T531	66
values[5]	41501	1			T539	11		T531	55		T540	167
values[6]	30475	1			T539	12		T531	62		T540	120
values[7]	24346	1			T539	5		T531	48		T540	117
values[8]	20563	1			T539	6		T531	36		T540	66
values[9]	17982	1			T539	11		T531	44		T540	102
values[10]	15812	1			T539	3		T531	38		T540	96
values[11]	14875	1			T539	1		T531	24		T540	79
values[12]	13932	1			T539	3		T531	52		T540	56
values[13]	13587	1			T539	1		T531	59		T540	46
values[14]	12973	1			T539	8		T531	50		T540	34
values[15]	12400	1			T539	12		T531	36		T540	30
values[16]	12029	1			T539	16		T531	27		T540	31
values[17]	11370	1			T539	9		T531	36		T540	22
values[18]	10469	1			T539	3		T531	34		T540	26
values[19]	9931	1			T531	35		T540	27		T552	66
values[20]	9839	1			T531	22		T540	30		T552	67
values[21]	9671	1			T531	22		T540	23		T552	102
values[22]	9250	1			T531	29		T540	23		T552	96
values[23]	9044	1			T531	23		T540	18		T552	89
values[24]	8768	1			T531	24		T540	27		T552	73
values[25]	8520	1			T531	18		T540	34		T552	80
values[26]	8309	1			T531	24		T540	34		T552	76
values[27]	7861	1			T531	22		T540	20		T552	52
values[28]	7587	1			T531	25		T540	24		T552	51
values[29]	7090	1			T531	18		T540	31		T552	48
values[30]	6575	1			T531	18		T540	27		T552	39
values[31]	6227	1			T531	12		T540	23		T552	61
values[32]	5681	1			T531	7		T540	23		T552	83
values[33]	5169	1			T531	4		T540	14		T552	48
values[34]	4854	1			T531	10		T540	20		T552	18
values[35]	4681	1			T531	10		T540	19		T552	14
values[36]	4410	1			T531	12		T540	21		T552	14
values[37]	4269	1			T531	8		T540	26		T552	7
values[38]	4089	1			T531	6		T540	16		T552	7
values[39]	3984	1			T531	13		T540	20		T552	15
values[40]	3803	1			T531	13		T540	31		T552	8
values[41]	3753	1			T531	10		T540	27		T552	4
values[42]	3749	1			T531	9		T540	55		T552	8
values[43]	3498	1			T531	7		T540	21		T552	7
values[44]	3400	1			T531	5		T540	18		T552	6
values[45]	3382	1			T531	8		T540	16		T552	3
values[46]	3364	1			T531	6		T540	13		T552	5
values[47]	3241	1			T531	17		T540	16		T552	10
values[48]	3199	1			T531	18		T540	13		T552	5
values[49]	3121	1			T531	16		T540	21		T552	9
values[50]	3012	1			T531	11		T540	21		T552	7
values[51]	2940	1			T531	16		T540	13		T552	11
values[52]	2863	1			T531	9		T540	12		T552	8
values[53]	2836	1			T531	15		T540	16		T552	2
values[54]	2779	1			T531	7		T540	10		T552	2
values[55]	2804	1			T531	12		T540	9		T552	1
values[56]	2788	1			T531	11		T540	17		T538	3
values[57]	2720	1			T531	5		T540	10		T538	3
values[58]	2713	1			T531	11		T540	14		T538	3
values[59]	2649	1			T531	7		T540	12		T538	3
values[60]	2567	1			T531	3		T540	7		T538	3
values[61]	2888	1			T531	4		T540	12		T538	3
values[62]	4514	1			T531	4		T540	35		T538	3
values[63]	12330	1			T531	5		T540	166		T538	3
values[64]	226674	1			T531	217		T540	451		T538	493

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4908373	1			T71	112		T72	2392		T73	619
values[2]	828075	1			T71	29		T72	620		T73	160
values[3]	88094	1			T71	11		T72	76		T73	29
values[4]	14605	1			T71	5		T72	3		T236	1
values[5]	5391	1			T71	1		T72	1		T236	1
values[6]	3358	1			T72	1		T539	5		T531	7
values[7]	2483	1			T531	4		T540	2		T538	1
values[8]	2076	1			T531	5		T540	2		T846	1
values[9]	2023	1			T531	3		T540	6		T846	1
values[10]	1849	1			T531	3		T540	6		T846	1
values[11]	1671	1			T531	3		T540	5		T846	1
values[12]	1635	1			T531	2		T540	11		T846	1
values[13]	1510	1			T531	2		T540	17		T846	1
values[14]	1353	1			T531	4		T540	14		T846	1
values[15]	1272	1			T531	2		T540	19		T846	1
values[16]	1216	1			T531	4		T540	7		T846	1
values[17]	1159	1			T531	3		T540	7		T846	1
values[18]	1037	1			T531	6		T540	4		T846	1
values[19]	893	1			T531	3		T540	4		T846	1
values[20]	919	1			T531	3		T540	13		T846	1
values[21]	963	1			T531	7		T540	8		T846	1
values[22]	962	1			T531	4		T540	18		T846	1
values[23]	871	1			T531	2		T540	6		T846	1
values[24]	792	1			T531	4		T540	5		T846	1
values[25]	800	1			T531	3		T540	14		T846	1
values[26]	810	1			T531	2		T540	16		T846	1
values[27]	757	1			T531	3		T540	10		T846	1
values[28]	737	1			T531	2		T540	8		T846	1
values[29]	675	1			T531	3		T540	3		T846	1
values[30]	656	1			T531	5		T540	1		T846	1
values[31]	661	1			T531	7		T540	2		T846	1
values[32]	598	1			T531	4		T540	2		T846	1
values[33]	615	1			T531	2		T540	2		T846	1
values[34]	593	1			T531	2		T540	4		T846	1
values[35]	594	1			T531	3		T540	1		T846	1
values[36]	549	1			T531	2		T540	1		T846	1
values[37]	503	1			T531	2		T540	1		T846	1
values[38]	498	1			T531	3		T540	2		T846	1
values[39]	518	1			T531	6		T540	3		T846	1
values[40]	526	1			T531	3		T540	1		T846	1
values[41]	556	1			T531	2		T540	3		T846	1
values[42]	552	1			T531	9		T540	4		T846	2
values[43]	482	1			T531	4		T540	1		T846	1
values[44]	529	1			T531	3		T540	2		T846	1
values[45]	502	1			T531	2		T540	6		T846	1
values[46]	501	1			T531	2		T540	1		T846	1
values[47]	438	1			T531	6		T540	1		T846	1
values[48]	443	1			T531	3		T540	1		T846	1
values[49]	424	1			T531	2		T540	2		T846	1
values[50]	450	1			T531	3		T540	2		T846	1
values[51]	407	1			T531	6		T540	3		T846	1
values[52]	415	1			T531	10		T540	1		T846	1
values[53]	409	1			T531	2		T540	3		T846	1
values[54]	394	1			T531	2		T540	1		T846	1
values[55]	382	1			T531	4		T540	1		T846	1
values[56]	369	1			T531	5		T540	2		T846	1
values[57]	369	1			T531	2		T540	2		T846	1
values[58]	355	1			T531	3		T540	3		T846	1
values[59]	343	1			T531	5		T540	1		T846	1
values[60]	378	1			T531	2		T540	1		T846	1
values[61]	441	1			T531	4		T540	1		T846	1
values[62]	683	1			T531	2		T540	5		T846	1
values[63]	2630	1			T531	19		T540	25		T846	1
values[64]	26108	1			T531	214		T540	97		T846	209

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	595365	1			T71	1		T72	23		T73	8
values[2]	2657181	1			T71	131		T72	708		T73	662
values[3]	1262110	1			T71	56		T72	1894		T73	223
values[4]	167618	1			T71	4		T72	64		T73	10
values[5]	85454	1			T72	1		T539	27		T531	88
values[6]	54761	1			T539	21		T531	68		T540	172
values[7]	39518	1			T539	10		T531	50		T540	137
values[8]	30816	1			T539	9		T531	60		T540	150
values[9]	25539	1			T539	5		T531	44		T540	103
values[10]	22060	1			T539	4		T531	27		T540	55
values[11]	19538	1			T539	2		T531	27		T540	53
values[12]	17921	1			T539	1		T531	30		T540	45
values[13]	16621	1			T539	5		T531	42		T540	39
values[14]	16129	1			T539	9		T531	54		T540	74
values[15]	15283	1			T539	8		T531	40		T540	52
values[16]	14330	1			T539	9		T531	45		T540	41
values[17]	13707	1			T539	12		T531	39		T540	59
values[18]	13515	1			T539	7		T531	37		T540	45
values[19]	13152	1			T539	6		T531	38		T540	39
values[20]	12811	1			T539	4		T531	34		T540	26
values[21]	12034	1			T539	3		T531	26		T540	25
values[22]	11195	1			T539	2		T531	31		T540	25
values[23]	10559	1			T539	1		T531	22		T540	20
values[24]	10387	1			T539	2		T531	35		T540	22
values[25]	9736	1			T539	2		T531	30		T540	36
values[26]	9229	1			T539	1		T531	30		T540	34
values[27]	8807	1			T539	1		T531	9		T540	43
values[28]	8248	1			T539	2		T531	14		T540	29
values[29]	7761	1			T539	3		T531	9		T540	25
values[30]	7264	1			T539	1		T531	4		T540	35
values[31]	6661	1			T539	1		T531	8		T540	27
values[32]	6122	1			T539	2		T531	4		T540	27
values[33]	5847	1			T539	5		T531	7		T540	16
values[34]	5535	1			T539	5		T531	8		T540	14
values[35]	5224	1			T539	6		T531	10		T540	23
values[36]	4953	1			T539	3		T531	8		T540	25
values[37]	4683	1			T539	1		T531	7		T540	19
values[38]	4327	1			T539	1		T531	10		T540	17
values[39]	4307	1			T539	5		T531	4		T540	17
values[40]	4201	1			T539	8		T531	3		T540	18
values[41]	4001	1			T539	5		T531	6		T540	19
values[42]	3885	1			T539	4		T531	4		T540	13
values[43]	3761	1			T539	5		T531	5		T540	16
values[44]	3752	1			T539	1		T531	2		T540	24
values[45]	3646	1			T539	3		T531	3		T540	21
values[46]	3583	1			T531	2		T540	22		T552	4
values[47]	3628	1			T531	13		T540	22		T552	4
values[48]	3502	1			T531	8		T540	20		T552	3
values[49]	3376	1			T531	3		T540	10		T552	2
values[50]	3460	1			T531	2		T540	7		T552	3
values[51]	3403	1			T531	4		T540	11		T552	6
values[52]	3248	1			T531	4		T540	13		T552	1
values[53]	3246	1			T531	7		T540	18		T552	1
values[54]	3239	1			T531	3		T540	16		T538	3
values[55]	3120	1			T531	3		T540	12		T538	3
values[56]	3098	1			T531	7		T540	14		T538	3
values[57]	2968	1			T531	6		T540	13		T538	3
values[58]	2914	1			T531	2		T540	11		T538	3
values[59]	2810	1			T531	2		T540	11		T538	3
values[60]	2793	1			T531	6		T540	11		T538	3
values[61]	2890	1			T531	2		T540	10		T538	3
values[62]	3991	1			T531	3		T540	44		T538	3
values[63]	10355	1			T531	2		T540	88		T538	3
values[64]	216643	1			T531	221		T540	257		T538	608