Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2314460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38664128

1

T1

6400

T2

10364

T3

4262

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28962212	1			T1	2809		T2	2512		T3	1272
values[0x0]	10513538	1			T1	3591		T2	7852		T3	2990
values[0x1]	1502838	1			T1	455		T2	269		T3	127

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	873912	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40104676

1

T1

6855

T2

10633

T3

4389

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19033930	1			T1	3428		T2	5318		T3	2195
valid_sources[0x01]	19032673	1			T1	3427		T2	5315		T3	2194
valid_sources[0x02]	47182	1			T216	2		T150	209		T151	133
valid_sources[0x03]	47125	1			T215	3		T150	192		T151	260
valid_sources[0x04]	47545	1			T215	4		T216	2		T150	204
valid_sources[0x05]	47213	1			T215	4		T216	2		T150	254
valid_sources[0x06]	47088	1			T215	1		T150	197		T151	163
valid_sources[0x07]	47383	1			T215	4		T225	2		T150	174
valid_sources[0x08]	46221	1			T225	3		T150	272		T151	105
valid_sources[0x09]	47109	1			T225	4		T150	235		T151	205
valid_sources[0x0a]	46055	1			T215	1		T150	192		T151	169
valid_sources[0x0b]	47532	1			T216	1		T225	1		T150	248
valid_sources[0x0c]	46486	1			T75	16		T76	39		T225	2
valid_sources[0x0d]	46916	1			T215	3		T225	1		T150	355
valid_sources[0x0e]	46684	1			T216	1		T150	287		T151	124
valid_sources[0x0f]	47189	1			T216	2		T150	216		T151	166
valid_sources[0x10]	46837	1			T150	285		T151	153		T543	6
valid_sources[0x11]	47053	1			T75	7		T150	336		T151	191
valid_sources[0x12]	46965	1			T215	1		T150	336		T151	155
valid_sources[0x13]	46594	1			T150	230		T151	150		T543	1
valid_sources[0x14]	46970	1			T215	1		T216	1		T150	267
valid_sources[0x15]	46746	1			T150	234		T151	167		T543	9
valid_sources[0x16]	47442	1			T216	1		T225	1		T150	238
valid_sources[0x17]	47144	1			T225	1		T150	277		T151	232
valid_sources[0x18]	46858	1			T75	1		T150	189		T151	133
valid_sources[0x19]	47900	1			T150	308		T151	100		T543	10
valid_sources[0x1a]	46335	1			T216	1		T150	206		T151	167
valid_sources[0x1b]	47266	1			T225	2		T150	348		T151	275
valid_sources[0x1c]	47200	1			T215	1		T150	304		T151	166
valid_sources[0x1d]	46162	1			T75	1		T216	1		T150	230
valid_sources[0x1e]	47441	1			T150	242		T151	224		T543	13
valid_sources[0x1f]	47075	1			T216	1		T150	237		T151	176
valid_sources[0x20]	47203	1			T216	1		T150	183		T151	177

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27953106

1

T1

2809

T2

2512

T3

1272

values[0x0]

all_enables

biggest_size

10455602

1

T1

3591

T2

7852

T3

2990

values[0x1]

all_enables

biggest_size

255420

1

T52

19

T75

22

T76

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2932110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

462972

1

T71

14

T72

342

T73

142

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1149885	1			T71	31		T72	865		T73	302
values[0x0]	1095678	1			T71	41		T72	870		T73	318
values[0x1]	1149519	1			T71	32		T72	920		T73	316

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2270602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1124480

1

T71

29

T72

857

T73

315

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53366	1			T72	41		T73	2		T77	3
valid_sources[0x01]	53377	1			T71	1		T72	35		T73	39
valid_sources[0x02]	52001	1			T71	9		T72	27		T73	6
valid_sources[0x03]	53923	1			T71	2		T72	59		T73	5
valid_sources[0x04]	52473	1			T72	49		T73	23		T77	1
valid_sources[0x05]	53405	1			T72	40		T73	10		T236	14
valid_sources[0x06]	53319	1			T72	76		T73	2		T236	24
valid_sources[0x07]	52631	1			T72	16		T73	15		T77	1
valid_sources[0x08]	52439	1			T71	2		T72	25		T73	1
valid_sources[0x09]	53055	1			T71	1		T72	27		T73	2
valid_sources[0x0a]	52635	1			T71	4		T72	31		T73	2
valid_sources[0x0b]	53732	1			T72	74		T73	11		T236	16
valid_sources[0x0c]	53438	1			T72	53		T73	2		T77	4
valid_sources[0x0d]	52852	1			T71	9		T72	23		T73	15
valid_sources[0x0e]	52740	1			T71	5		T72	45		T73	31
valid_sources[0x0f]	52677	1			T71	1		T72	18		T73	58
valid_sources[0x10]	52816	1			T71	1		T72	33		T73	3
valid_sources[0x11]	53075	1			T71	1		T72	26		T73	4
valid_sources[0x12]	53230	1			T71	1		T72	45		T73	37
valid_sources[0x13]	52994	1			T71	2		T72	20		T73	16
valid_sources[0x14]	52806	1			T71	4		T72	22		T73	3
valid_sources[0x15]	53294	1			T72	52		T73	25		T236	16
valid_sources[0x16]	52706	1			T71	1		T72	81		T73	8
valid_sources[0x17]	53217	1			T71	2		T72	35		T73	25
valid_sources[0x18]	54125	1			T71	2		T72	63		T73	26
valid_sources[0x19]	52664	1			T72	54		T73	5		T236	22
valid_sources[0x1a]	53719	1			T71	3		T72	20		T73	14
valid_sources[0x1b]	53215	1			T71	1		T72	42		T73	23
valid_sources[0x1c]	52696	1			T72	45		T73	3		T236	20
valid_sources[0x1d]	53888	1			T72	25		T73	5		T77	2
valid_sources[0x1e]	53492	1			T71	10		T72	46		T73	28
valid_sources[0x1f]	52808	1			T72	16		T73	20		T236	15
valid_sources[0x20]	53419	1			T72	73		T73	8		T77	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48481

1

T71

1

T72

29

T73

11

values[0x0]

all_enables

biggest_size

365779

1

T71

10

T72

279

T73

112

values[0x1]

all_enables

biggest_size

48712

1

T71

3

T72

34

T73

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3134319	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

510290

1

T71

24

T72

446

T73

117

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1247072	1			T71	47		T72	1038		T73	275
values[0x0]	1148609	1			T71	45		T72	1001		T73	254
values[0x1]	1248928	1			T71	66		T72	1054		T73	279

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2404939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1239670

1

T71

57

T72

1060

T73

274

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57269	1			T72	56		T73	7		T236	8
valid_sources[0x01]	58482	1			T71	12		T72	71		T73	20
valid_sources[0x02]	57147	1			T71	1		T72	51		T73	5
valid_sources[0x03]	57188	1			T71	1		T72	40		T73	23
valid_sources[0x04]	57127	1			T72	44		T73	8		T236	19
valid_sources[0x05]	56852	1			T71	3		T72	55		T73	35
valid_sources[0x06]	56299	1			T72	58		T73	6		T77	1
valid_sources[0x07]	56950	1			T71	3		T72	45		T73	4
valid_sources[0x08]	56478	1			T71	2		T72	50		T73	3
valid_sources[0x09]	57022	1			T71	5		T72	49		T73	4
valid_sources[0x0a]	56736	1			T71	4		T72	63		T73	22
valid_sources[0x0b]	56996	1			T71	6		T72	49		T73	23
valid_sources[0x0c]	57737	1			T72	44		T73	21		T236	9
valid_sources[0x0d]	57129	1			T71	3		T72	43		T73	5
valid_sources[0x0e]	57394	1			T71	3		T72	45		T73	31
valid_sources[0x0f]	55735	1			T72	45		T73	5		T236	4
valid_sources[0x10]	57462	1			T72	55		T73	5		T236	16
valid_sources[0x11]	55953	1			T71	2		T72	42		T73	18
valid_sources[0x12]	56963	1			T71	3		T72	39		T73	15
valid_sources[0x13]	56727	1			T71	1		T72	47		T73	14
valid_sources[0x14]	56569	1			T71	3		T72	47		T73	18
valid_sources[0x15]	57572	1			T71	4		T72	50		T73	3
valid_sources[0x16]	55330	1			T71	5		T72	45		T73	8
valid_sources[0x17]	56903	1			T72	44		T73	6		T235	1
valid_sources[0x18]	57290	1			T71	1		T72	42		T73	12
valid_sources[0x19]	57937	1			T71	4		T72	56		T73	4
valid_sources[0x1a]	56820	1			T71	4		T72	45		T73	44
valid_sources[0x1b]	56491	1			T72	42		T73	8		T77	2
valid_sources[0x1c]	56584	1			T71	3		T72	62		T73	6
valid_sources[0x1d]	57890	1			T71	3		T72	45		T73	22
valid_sources[0x1e]	57501	1			T71	1		T72	54		T73	9
valid_sources[0x1f]	57172	1			T72	58		T73	4		T77	3
valid_sources[0x20]	56503	1			T72	47		T73	15		T77	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53444

1

T71

2

T72

45

T73

6

values[0x0]

all_enables

biggest_size

402964

1

T71

18

T72

367

T73

95

values[0x1]

all_enables

biggest_size

53882

1

T71

4

T72

34

T73

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2965702	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

468067

1

T71

31

T72

374

T73

124

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1161581	1			T71	67		T72	912		T73	283
values[0x0]	1110033	1			T71	59		T72	908		T73	303
values[0x1]	1162155	1			T71	66		T72	870		T73	317

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2296980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1136789

1

T71

63

T72

905

T73

279

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53919	1			T71	8		T72	38		T73	19
valid_sources[0x01]	53157	1			T71	2		T72	44		T73	1
valid_sources[0x02]	53221	1			T71	2		T72	18		T77	1
valid_sources[0x03]	52894	1			T71	5		T72	23		T73	4
valid_sources[0x04]	53321	1			T71	6		T72	80		T73	6
valid_sources[0x05]	53989	1			T71	2		T72	43		T73	5
valid_sources[0x06]	53649	1			T71	1		T72	46		T73	31
valid_sources[0x07]	53115	1			T71	6		T72	28		T73	13
valid_sources[0x08]	53230	1			T71	9		T72	29		T73	22
valid_sources[0x09]	53981	1			T71	1		T72	49		T73	33
valid_sources[0x0a]	53779	1			T71	4		T72	41		T73	33
valid_sources[0x0b]	54084	1			T71	5		T72	37		T73	4
valid_sources[0x0c]	53646	1			T72	45		T73	8		T236	13
valid_sources[0x0d]	54075	1			T71	6		T72	61		T73	26
valid_sources[0x0e]	53360	1			T71	2		T72	63		T73	16
valid_sources[0x0f]	53307	1			T71	1		T72	39		T73	18
valid_sources[0x10]	54025	1			T71	4		T72	59		T73	22
valid_sources[0x11]	54040	1			T71	4		T72	35		T73	11
valid_sources[0x12]	53453	1			T71	2		T72	61		T73	19
valid_sources[0x13]	53287	1			T71	4		T72	37		T73	11
valid_sources[0x14]	54102	1			T71	3		T72	72		T73	19
valid_sources[0x15]	53686	1			T71	1		T72	37		T73	4
valid_sources[0x16]	53637	1			T72	17		T73	5		T77	3
valid_sources[0x17]	53313	1			T72	30		T73	15		T77	4
valid_sources[0x18]	54522	1			T71	3		T72	37		T73	22
valid_sources[0x19]	54181	1			T71	1		T72	24		T73	26
valid_sources[0x1a]	54551	1			T71	4		T72	18		T73	12
valid_sources[0x1b]	53903	1			T71	3		T72	50		T73	9
valid_sources[0x1c]	53304	1			T71	2		T72	45		T73	14
valid_sources[0x1d]	54603	1			T71	3		T72	43		T73	2
valid_sources[0x1e]	53286	1			T71	4		T72	49		T73	8
valid_sources[0x1f]	53266	1			T71	1		T72	39		T73	12
valid_sources[0x20]	53350	1			T71	1		T72	60		T73	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49313

1

T71

3

T72

44

T73

12

values[0x0]

all_enables

biggest_size

369565

1

T71

21

T72

298

T73

97

values[0x1]

all_enables

biggest_size

49189

1

T71

7

T72

32

T73

15