Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	542445574	63186365	0	0
DepthKnown_A	542445574	542337371	0	0
RvalidKnown_A	542445574	542337371	0	0
WreadyKnown_A	542445574	542337371	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	63186365	0	0
T1	197955	15694	0	0
T2	231310	19669	0	0
T3	714353	101045	0	0
T4	101890	62264	0	0
T5	537765	63457	0	0
T6	118847	130813	0	0
T7	435656	37924	0	0
T21	155692	11496	0	0
T86	157831	21339	0	0
T87	506792	71328	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	542445574	49144911	0	0
DepthKnown_A	542445574	542337371	0	0
RvalidKnown_A	542445574	542337371	0	0
WreadyKnown_A	542445574	542337371	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	49144911	0	0
T1	197955	12324	0	0
T2	231310	13933	0	0
T3	714353	97919	0	0
T4	101890	30732	0	0
T5	537765	45921	0	0
T6	118847	113112	0	0
T7	435656	30397	0	0
T21	155692	8831	0	0
T86	157831	16156	0	0
T87	506792	68066	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	542445574	44945271	0	0
DepthKnown_A	542445574	542337371	0	0
RvalidKnown_A	542445574	542337371	0	0
WreadyKnown_A	542445574	542337371	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	44945271	0	0
T1	197955	7029	0	0
T2	231310	11042	0	0
T3	714353	4542	0	0
T4	101890	6888	0	0
T5	537765	26429	0	0
T6	118847	177508	0	0
T7	435656	23288	0	0
T21	155692	6385	0	0
T86	157831	9526	0	0
T87	506792	7179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	542445574	38057822	0	0
DepthKnown_A	542445574	542337371	0	0
RvalidKnown_A	542445574	542337371	0	0
WreadyKnown_A	542445574	542337371	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	38057822	0	0
T1	197955	6855	0	0
T2	231310	10633	0	0
T3	714353	4389	0	0
T4	101890	6227	0	0
T5	537765	25593	0	0
T6	118847	105227	0	0
T7	435656	22780	0	0
T21	155692	6077	0	0
T86	157831	9248	0	0
T87	506792	7019	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	542337371	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	640142009	97189	0	0
DepthKnown_A	640142009	640018177	0	0
RvalidKnown_A	640142009	640018177	0	0
WreadyKnown_A	640142009	640018177	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	97189	0	0
T1	197955	25	0	0
T2	231310	49	0	0
T3	714353	22	0	0
T4	101890	34	0	0
T5	537765	112	0	0
T6	118847	27	0	0
T7	435656	68	0	0
T21	155692	69	0	0
T86	157831	26	0	0
T87	506792	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	640142009	100907	0	0
DepthKnown_A	640142009	640018177	0	0
RvalidKnown_A	640142009	640018177	0	0
WreadyKnown_A	640142009	640018177	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	100907	0	0
T1	197955	25	0	0
T2	231310	49	0	0
T3	714353	22	0	0
T4	101890	34	0	0
T5	537765	112	0	0
T6	118847	27	0	0
T7	435656	68	0	0
T21	155692	69	0	0
T86	157831	26	0	0
T87	506792	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	640142009	53419	0	0
DepthKnown_A	640142009	640018177	0	0
RvalidKnown_A	640142009	640018177	0	0
WreadyKnown_A	640142009	640018177	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	53419	0	0
T1	197955	22	0	0
T2	231310	46	0	0
T3	714353	12	0	0
T4	101890	31	0	0
T5	537765	97	0	0
T6	118847	0	0	0
T7	435656	64	0	0
T21	155692	68	0	0
T46	0	8	0	0
T86	157831	23	0	0
T87	506792	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	640142009	53419	0	0
DepthKnown_A	640142009	640018177	0	0
RvalidKnown_A	640142009	640018177	0	0
WreadyKnown_A	640142009	640018177	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	53419	0	0
T1	197955	22	0	0
T2	231310	46	0	0
T3	714353	12	0	0
T4	101890	31	0	0
T5	537765	97	0	0
T6	118847	0	0	0
T7	435656	64	0	0
T21	155692	68	0	0
T46	0	8	0	0
T86	157831	23	0	0
T87	506792	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	640142009	43770	0	0
DepthKnown_A	640142009	640018177	0	0
RvalidKnown_A	640142009	640018177	0	0
WreadyKnown_A	640142009	640018177	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	43770	0	0
T1	197955	3	0	0
T2	231310	3	0	0
T3	714353	10	0	0
T4	101890	3	0	0
T5	537765	15	0	0
T6	118847	27	0	0
T7	435656	4	0	0
T21	155692	1	0	0
T86	157831	3	0	0
T87	506792	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	640142009	47488	0	0
DepthKnown_A	640142009	640018177	0	0
RvalidKnown_A	640142009	640018177	0	0
WreadyKnown_A	640142009	640018177	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	47488	0	0
T1	197955	3	0	0
T2	231310	3	0	0
T3	714353	10	0	0
T4	101890	3	0	0
T5	537765	15	0	0
T6	118847	27	0	0
T7	435656	4	0	0
T21	155692	1	0	0
T86	157831	3	0	0
T87	506792	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640142009	640018177	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0