Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T52,*T74,*T75	Yes	T52,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T52,T75,T76	Yes	T52,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	INPUT
tl_o.a_ready	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T273,*T76,*T761	Yes	T273,T76,T761	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T41,*T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T166,T705,T168	Yes	T166,T705,T168	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T166,T81,T82	Yes	T166,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T166,T81,T82	Yes	T166,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T166,T705,T168	Yes	T166,T705,T168	OUTPUT
cio_rx_i	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T154,T228,T102	Yes	T154,T228,T102	OUTPUT
intr_tx_empty_o	Yes	Yes	T154,T228,T102	Yes	T154,T228,T102	OUTPUT
intr_rx_watermark_o	Yes	Yes	T154,T228,T102	Yes	T154,T228,T102	OUTPUT
intr_tx_done_o	Yes	Yes	T154,T228,T102	Yes	T154,T228,T102	OUTPUT
intr_rx_overflow_o	Yes	Yes	T154,T228,T102	Yes	T154,T228,T102	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_break_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_timeout_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T52,*T74,*T75	Yes	T52,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T52,T75,T76	Yes	T52,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	INPUT
tl_o.a_ready	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T273,*T76,*T761	Yes	T273,T76,T761	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T41,*T43	Yes	T6,T41,T43	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T168,T416,T762	Yes	T168,T416,T762	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T82,T83,T331	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T331	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T168,T416,T762	Yes	T168,T416,T762	OUTPUT
cio_rx_i	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T102,T263,T231	Yes	T102,T263,T231	OUTPUT
intr_tx_empty_o	Yes	Yes	T102,T231,T232	Yes	T102,T231,T232	OUTPUT
intr_rx_watermark_o	Yes	Yes	T102,T231,T232	Yes	T102,T231,T232	OUTPUT
intr_tx_done_o	Yes	Yes	T102,T353,T231	Yes	T102,T353,T231	OUTPUT
intr_rx_overflow_o	Yes	Yes	T102,T353,T231	Yes	T102,T353,T231	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_break_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_timeout_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T52,*T74,*T75	Yes	T52,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T52,T75,T76	Yes	T52,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	INPUT
tl_o.a_ready	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T72,*T73	Yes	T76,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T228,*T229,*T123	Yes	T228,T229,T123	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T166,T168,T763	Yes	T166,T168,T763	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T166,T81,T82	Yes	T166,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T166,T81,T82	Yes	T166,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T166,T168,T763	Yes	T166,T168,T763	OUTPUT
cio_rx_i	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	INPUT
cio_tx_o	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
intr_tx_empty_o	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
intr_rx_watermark_o	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
intr_tx_done_o	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
intr_rx_overflow_o	Yes	Yes	T228,T229,T123	Yes	T228,T229,T123	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_break_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_timeout_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T52,*T74,*T75	Yes	T52,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T52,T75,T76	Yes	T52,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T154,T168,T348	Yes	T154,T168,T348	INPUT
tl_o.a_ready	Yes	Yes	T154,T168,T348	Yes	T154,T168,T348	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T154,T168,T348	Yes	T154,T168,T348	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T154,T168,T348	Yes	T154,T168,T348	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T72,*T73	Yes	T76,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T154,*T348,*T349	Yes	T154,T348,T349	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T154,T168,T348	Yes	T154,T168,T348	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T168,T409,T47	Yes	T168,T409,T47	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T168,T409,T47	Yes	T168,T409,T47	OUTPUT
cio_rx_i	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	INPUT
cio_tx_o	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	OUTPUT
intr_tx_empty_o	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	OUTPUT
intr_rx_watermark_o	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	OUTPUT
intr_tx_done_o	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	OUTPUT
intr_rx_overflow_o	Yes	Yes	T154,T348,T349	Yes	T154,T348,T349	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_break_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_timeout_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T297,T337,T335	Yes	T297,T337,T335	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T297,T337,T335	Yes	T297,T337,T335	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T52,*T74,*T75	Yes	T52,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T52,T75,T76	Yes	T52,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T168,T297,T337	Yes	T168,T297,T337	INPUT
tl_o.a_ready	Yes	Yes	T168,T297,T337	Yes	T168,T297,T337	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T297,T337,T335	Yes	T297,T337,T335	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T168,T297,T337	Yes	T168,T297,T337	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T168,T297,T337	Yes	T168,T297,T337	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T72,*T73	Yes	T76,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T297,*T337,*T335	Yes	T297,T337,T335	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T168,T297,T337	Yes	T168,T297,T337	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T705,T168,T47	Yes	T705,T168,T47	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T705,T168,T47	Yes	T705,T168,T47	OUTPUT
cio_rx_i	Yes	Yes	T297,T337,T338	Yes	T297,T337,T338	INPUT
cio_tx_o	Yes	Yes	T297,T337,T338	Yes	T297,T337,T338	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T297,T337,T335	Yes	T297,T337,T335	OUTPUT
intr_tx_empty_o	Yes	Yes	T297,T337,T335	Yes	T297,T337,T335	OUTPUT
intr_rx_watermark_o	Yes	Yes	T297,T337,T335	Yes	T297,T337,T335	OUTPUT
intr_tx_done_o	Yes	Yes	T297,T337,T335	Yes	T297,T337,T335	OUTPUT
intr_rx_overflow_o	Yes	Yes	T297,T337,T335	Yes	T297,T337,T335	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_break_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_timeout_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T335,T336,T352	Yes	T335,T336,T352	OUTPUT

*Tests covering at least one bit in the range