Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T5,T104,T234	Yes	T5,T104,T234	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T59,T104	Yes	T5,T59,T104	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T52,T75,T76	Yes	T52,T75,T76	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T215,T73,T77	Yes	T215,T73,T77	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T215,T71,T72	Yes	T215,T71,T72	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T5,T59,T60	Yes	T5,T59,T60	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T46,T45,T63	Yes	T46,T45,T63	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T46,T45,T63	Yes	T46,T45,T63	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T46,T45,T63	Yes	T46,T45,T63	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T46,T45,T63	Yes	T46,T45,T63	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T46,T45,T63	Yes	T46,T45,T63	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T46,T45,T63	Yes	T46,T45,T63	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T46,*T45,*T63	Yes	T46,T45,T63	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T46,T45,T63	Yes	T46,T45,T63	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T52,T71,T72	Yes	T52,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T52,T72,T73	Yes	T52,T71,T72	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T72,T73,T77	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T52,*T71,*T72	Yes	T52,T71,T72	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T52,T74,T273	Yes	T52,T74,T273	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T74,T273	Yes	T52,T74,T273	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T52,T74,T273	Yes	T52,T74,T273	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T52,T74,T273	Yes	T52,T74,T273	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T52,T74,T273	Yes	T52,T74,T273	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T74,*T273,*T274	Yes	T74,T273,T274	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T52,T74,T273	Yes	T52,T74,T273	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T6,T5	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T74,T273,T274	Yes	T74,T273,T274	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T74,T273	Yes	T52,T74,T273	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T6,T5	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T74,*T273,*T274	Yes	T74,T273,T274	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T6,T5	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T52,T74,T273	Yes	T52,T74,T273	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T6,T46,T41	Yes	T6,T46,T41	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T47,T48	Yes	T52,T47,T48	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T375,T286,T52	Yes	T375,T286,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T375,T286,T52	Yes	T375,T286,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T52,T47,T48	Yes	T52,T47,T48	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T375,T286,T52	Yes	T375,T286,T52	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T52,*T71,*T72	Yes	T52,T71,T72	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T375,T286,T52	Yes	T375,T286,T52	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T375,T286,T52	Yes	T375,T286,T52	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T286,T287,T425	Yes	T286,T287,T425	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T71,T72	Yes	T52,T47,T48	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T286,T52,T287	Yes	T286,T52,T287	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T72,T73,T77	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T52,*T72,*T73	Yes	T52,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T72,T73,T77	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T375,*T286,*T52	Yes	T375,T286,T52	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T375,T286,T52	Yes	T375,T286,T52	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T52,*T74,*T75	Yes	T52,T74,T75	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T52,T75,T76	Yes	T52,T75,T76	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T104,T365,T705	Yes	T104,T365,T705	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T52,*T74,*T75	Yes	T52,T74,T75	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T11,T263,T12	Yes	T11,T263,T12	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T168	Yes	T11,T12,T168	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T11,T263,T12	Yes	T11,T263,T12	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T11,T263,T12	Yes	T11,T263,T12	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T11,T12,T168	Yes	T11,T12,T168	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T11,T263,T12	Yes	T11,T263,T12	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T12,T209,T210	Yes	T12,T209,T210	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T11,T263,T12	Yes	T11,T263,T12	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T11,T263,T12	Yes	T11,T263,T12	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T71,T72,T73	Yes	T72,T73,T77	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T395	Yes	T11,T12,T395	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T263,T12	Yes	T11,T263,T12	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T11,T12,T395	Yes	T11,T12,T395	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T71,T72	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T11,*T263,*T12	Yes	T11,T263,T12	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T11,T263,T12	Yes	T11,T263,T12	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T263,T395,T162	Yes	T263,T395,T162	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T395,T162,T397	Yes	T395,T162,T397	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T263,T395,T162	Yes	T263,T395,T162	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T263,T395,T162	Yes	T263,T395,T162	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T395,T162,T397	Yes	T395,T162,T397	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T263,T395,T162	Yes	T263,T395,T162	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T263,T395,T162	Yes	T263,T395,T162	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T263,T395,T162	Yes	T263,T395,T162	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T395,T162,T397	Yes	T395,T162,T397	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T263,T395,T162	Yes	T263,T395,T162	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T395,T162,T397	Yes	T395,T162,T397	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T71,T72	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T263,*T395,*T162	Yes	T263,T395,T162	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T263,T395,T162	Yes	T263,T395,T162	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T17,T18,T263	Yes	T17,T18,T263	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T263	Yes	T17,T18,T263	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T18,T263	Yes	T17,T18,T263	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T17,T18,T263	Yes	T17,T18,T263	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T17,T18,T263	Yes	T17,T18,T263	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T76,*T71,*T72	Yes	T76,T71,T72	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T17,T18,T263	Yes	T17,T18,T263	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T17,T18,T263	Yes	T17,T18,T263	INPUT
tl_usbdev_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T263,T395,T68	Yes	T263,T395,T68	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T263,T395,T68	Yes	T263,T395,T68	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T17,T18,T263	Yes	T17,T18,T263	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T76,*T72,*T73	Yes	T76,T71,T72	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T17,*T18,*T263	Yes	T17,T18,T263	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T17,T18,T263	Yes	T17,T18,T263	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T6,T5	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T6,T4	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T72,T73,T77	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T71,T72	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T225,T72,T73	Yes	T225,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T225,T71,T72	Yes	T225,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T225,T72,T73	Yes	T225,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T225,T71,T72	Yes	T225,T71,T72	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T6,T5	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T408,T361,T419	Yes	T408,T361,T419	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	INPUT
tl_hmac_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	INPUT
tl_hmac_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T71,T72	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T6,*T41,*T408	Yes	T6,T41,T408	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T6,T41,T408	Yes	T6,T41,T408	INPUT
tl_kmac_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T132,T161,T101	Yes	T132,T161,T101	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T187,T132,T161	Yes	T187,T132,T161	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T187,T132,T161	Yes	T187,T132,T161	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T132,T161,T101	Yes	T132,T161,T101	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T187,T132,T161	Yes	T187,T132,T161	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T448,T240,T449	Yes	T448,T240,T449	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T187,T132,T161	Yes	T187,T132,T161	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T187,T132,T161	Yes	T187,T132,T161	INPUT
tl_kmac_i.d_error	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T187,T132,T161	Yes	T187,T132,T161	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T187,T132,T161	Yes	T187,T132,T161	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T132,T161,T101	Yes	T162,T448,T239	INPUT
tl_kmac_i.d_sink	Yes	Yes	T72,T73,T77	Yes	T71,T72,T73	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T72,T73	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T71,T72,T73	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T132,*T161,*T101	Yes	T162,T448,T239	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T187,T132,T161	Yes	T187,T132,T161	INPUT
tl_aes_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T734,T103,T735	Yes	T734,T103,T735	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T734,T103,T735	Yes	T734,T103,T735	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T130,T187,T131	Yes	T130,T187,T131	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T734,T103,T735	Yes	T734,T103,T735	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T130,T187,T131	Yes	T130,T187,T131	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T130,T187,T131	Yes	T130,T187,T131	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T130,T131,T734	Yes	T130,T131,T734	INPUT
tl_aes_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T130,T131,T734	Yes	T130,T131,T734	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T130,T131,T734	Yes	T130,T131,T734	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T130,T131,T734	Yes	T130,T131,T734	INPUT
tl_aes_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T130,*T131,*T734	Yes	T130,T131,T734	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T130,T131,T734	Yes	T130,T131,T734	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T72,T73,T77	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T72,T73	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T130,*T131,*T132	Yes	T130,T43,T131	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T71,T72	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T130,*T131,*T132	Yes	T130,T131,T132	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T71,T72	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T130,*T131,*T132	Yes	T130,T131,T132	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	INPUT
tl_edn1_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	INPUT
tl_edn1_i.d_sink	Yes	Yes	T72,T73,T77	Yes	T71,T72,T73	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T130,*T131,*T132	Yes	T130,T131,T132	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T130,T131,T132	Yes	T130,T131,T132	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T72,T73,T77	Yes	T71,T72,T73	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T72,T73,T77	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T71,T72	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T71,T72,T73	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_otbn_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T75,*T215,*T216	Yes	T75,T215,T216	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	INPUT
tl_otbn_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	INPUT
tl_otbn_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T75,*T215,*T216	Yes	T75,T215,T216	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T6,*T41,*T130	Yes	T6,T41,T130	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T6,T41,T130	Yes	T6,T41,T130	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T43,T132,T161	Yes	T43,T132,T161	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T43,T132,T161	Yes	T43,T132,T161	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T43,T132,T161	Yes	T43,T132,T161	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T132,T161,T101	Yes	T132,T161,T101	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T43,T132,T161	Yes	T43,T132,T161	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T225,*T71,*T72	Yes	T225,T71,T72	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T43,T132,T161	Yes	T43,T132,T161	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T43,T132,T161	Yes	T43,T132,T161	INPUT
tl_keymgr_i.d_error	Yes	Yes	T72,T77,T235	Yes	T72,T77,T236	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T132,T161,T101	Yes	T132,T161,T101	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T43,T132,T161	Yes	T43,T132,T161	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T43,T132,T161	Yes	T43,T132,T161	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T71,T72	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T72,T73,T77	Yes	T72,T73,T77	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T43,*T132,*T161	Yes	T43,T132,T161	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T43,T132,T161	Yes	T43,T132,T161	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T52,*T71,*T72	Yes	T52,T71,T72	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T52,T71,T72	Yes	T52,T71,T72	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T52,*T71,*T72	Yes	T52,T71,T72	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T2,T6,T5	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T225,*T439,*T71	Yes	T225,T439,T71	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T72,T73,T77	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T317,T318,T319	Yes	T317,T318,T319	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T42	Yes	T6,T41,T43	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T6,T41,T42	Yes	T6,T41,T43	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T225,*T72,*T73	Yes	T225,T439,T71	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T192,*T317,*T194	Yes	T440,T299,T262	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T6,T41,T43	Yes	T6,T41,T43	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T6,T5	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range