Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T197,T52,T313
0	1	Covered	T197,T313,T315
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T197,T313,T315
1	Covered	T197,T52,T313

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T197,T313,T315
1	Covered	T197,T52,T313

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T197,T313,T315
1	1	Covered	T197,T313,T315

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T197,T52,T313
1	0	Covered	T197,T313,T315
1	1	Covered	T197,T313,T315

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T197,T313,T315

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T197,T52,T313
0	Covered	T197,T313,T315

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T197,T52,T313
0	Covered	T197,T313,T315

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1084891148	1068702822	0	0
CheckNGreaterZero_A	2048	2048	0	0
GntImpliesReady_A	1084891148	8362	0	0
GntImpliesValid_A	1084891148	8362	0	0
GrantKnown_A	1084891148	1068702822	0	0
IdxKnown_A	1084891148	1068702822	0	0
IndexIsCorrect_A	1084891148	8362	0	0
NoReadyValidNoGrant_A	1084891148	0	0	0
Priority_A	1084891148	8362	0	0
ReadyAndValidImplyGrant_A	1084891148	8362	0	0
ReqAndReadyImplyGrant_A	1084891148	8362	0	0
ReqImpliesValid_A	1084891148	8362	0	0
ValidKnown_A	1084891148	1068702822	0	0
gen_data_port_assertion.DataFlow_A	1084891148	8362	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	1068702822	0	0
T1	395910	395808	0	0
T2	462620	462212	0	0
T3	1428706	1428590	0	0
T4	203780	203670	0	0
T5	1075530	1074990	0	0
T6	237694	237670	0	0
T7	871312	870634	0	0
T21	311384	311268	0	0
T86	315662	315546	0	0
T87	1013584	1013460	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2048	2048	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T21	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	8362	0	0
T197	169294	2795	0	0
T258	597024	0	0	0
T297	220628	0	0	0
T298	195882	0	0	0
T313	0	2786	0	0
T315	0	2781	0	0
T360	375580	0	0	0
T415	570168	0	0	0
T416	496586	0	0	0
T417	508790	0	0	0
T418	776936	0	0	0
T419	485002	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	8362	0	0
T197	169294	2795	0	0
T258	597024	0	0	0
T297	220628	0	0	0
T298	195882	0	0	0
T313	0	2786	0	0
T315	0	2781	0	0
T360	375580	0	0	0
T415	570168	0	0	0
T416	496586	0	0	0
T417	508790	0	0	0
T418	776936	0	0	0
T419	485002	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	1068702822	0	0
T1	395910	395808	0	0
T2	462620	462212	0	0
T3	1428706	1428590	0	0
T4	203780	203670	0	0
T5	1075530	1074990	0	0
T6	237694	237670	0	0
T7	871312	870634	0	0
T21	311384	311268	0	0
T86	315662	315546	0	0
T87	1013584	1013460	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	1068702822	0	0
T1	395910	395808	0	0
T2	462620	462212	0	0
T3	1428706	1428590	0	0
T4	203780	203670	0	0
T5	1075530	1074990	0	0
T6	237694	237670	0	0
T7	871312	870634	0	0
T21	311384	311268	0	0
T86	315662	315546	0	0
T87	1013584	1013460	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	8362	0	0
T197	169294	2795	0	0
T258	597024	0	0	0
T297	220628	0	0	0
T298	195882	0	0	0
T313	0	2786	0	0
T315	0	2781	0	0
T360	375580	0	0	0
T415	570168	0	0	0
T416	496586	0	0	0
T417	508790	0	0	0
T418	776936	0	0	0
T419	485002	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	8362	0	0
T197	169294	2795	0	0
T258	597024	0	0	0
T297	220628	0	0	0
T298	195882	0	0	0
T313	0	2786	0	0
T315	0	2781	0	0
T360	375580	0	0	0
T415	570168	0	0	0
T416	496586	0	0	0
T417	508790	0	0	0
T418	776936	0	0	0
T419	485002	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	8362	0	0
T197	169294	2795	0	0
T258	597024	0	0	0
T297	220628	0	0	0
T298	195882	0	0	0
T313	0	2786	0	0
T315	0	2781	0	0
T360	375580	0	0	0
T415	570168	0	0	0
T416	496586	0	0	0
T417	508790	0	0	0
T418	776936	0	0	0
T419	485002	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	8362	0	0
T197	169294	2795	0	0
T258	597024	0	0	0
T297	220628	0	0	0
T298	195882	0	0	0
T313	0	2786	0	0
T315	0	2781	0	0
T360	375580	0	0	0
T415	570168	0	0	0
T416	496586	0	0	0
T417	508790	0	0	0
T418	776936	0	0	0
T419	485002	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	8362	0	0
T197	169294	2795	0	0
T258	597024	0	0	0
T297	220628	0	0	0
T298	195882	0	0	0
T313	0	2786	0	0
T315	0	2781	0	0
T360	375580	0	0	0
T415	570168	0	0	0
T416	496586	0	0	0
T417	508790	0	0	0
T418	776936	0	0	0
T419	485002	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	1068702822	0	0
T1	395910	395808	0	0
T2	462620	462212	0	0
T3	1428706	1428590	0	0
T4	203780	203670	0	0
T5	1075530	1074990	0	0
T6	237694	237670	0	0
T7	871312	870634	0	0
T21	311384	311268	0	0
T86	315662	315546	0	0
T87	1013584	1013460	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1084891148	8362	0	0
T197	169294	2795	0	0
T258	597024	0	0	0
T297	220628	0	0	0
T298	195882	0	0	0
T313	0	2786	0	0
T315	0	2781	0	0
T360	375580	0	0	0
T415	570168	0	0	0
T416	496586	0	0	0
T417	508790	0	0	0
T418	776936	0	0	0
T419	485002	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T197,T52,T313
0	1	Covered	T197,T313,T315
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T197,T313,T315
1	Covered	T197,T52,T313

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T197,T313,T315
1	Covered	T197,T52,T313

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T197,T313,T315
1	1	Covered	T197,T313,T315

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T197,T52,T313
1	0	Covered	T197,T313,T315
1	1	Covered	T197,T313,T315

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T197,T313,T315

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T197,T52,T313
0	Covered	T197,T313,T315

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T197,T52,T313
0	Covered	T197,T313,T315

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	542445574	534351411	0	0
CheckNGreaterZero_A	1024	1024	0	0
GntImpliesReady_A	542445574	5172	0	0
GntImpliesValid_A	542445574	5172	0	0
GrantKnown_A	542445574	534351411	0	0
IdxKnown_A	542445574	534351411	0	0
IndexIsCorrect_A	542445574	5172	0	0
NoReadyValidNoGrant_A	542445574	0	0	0
Priority_A	542445574	5172	0	0
ReadyAndValidImplyGrant_A	542445574	5172	0	0
ReqAndReadyImplyGrant_A	542445574	5172	0	0
ReqImpliesValid_A	542445574	5172	0	0
ValidKnown_A	542445574	534351411	0	0
gen_data_port_assertion.DataFlow_A	542445574	5172	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	534351411	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	5172	0	0
T197	84647	1732	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1722	0	0
T315	0	1718	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	5172	0	0
T197	84647	1732	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1722	0	0
T315	0	1718	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	534351411	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	534351411	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	5172	0	0
T197	84647	1732	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1722	0	0
T315	0	1718	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	5172	0	0
T197	84647	1732	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1722	0	0
T315	0	1718	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	5172	0	0
T197	84647	1732	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1722	0	0
T315	0	1718	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	5172	0	0
T197	84647	1732	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1722	0	0
T315	0	1718	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	5172	0	0
T197	84647	1732	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1722	0	0
T315	0	1718	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	534351411	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	5172	0	0
T197	84647	1732	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1722	0	0
T315	0	1718	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T197,T52,T313
0	1	Covered	T197,T313,T315
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T197,T313,T315
1	Covered	T197,T52,T313

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T197,T313,T315
1	Covered	T197,T52,T313

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T197,T313,T315
1	1	Covered	T197,T313,T315

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T197,T52,T313
1	0	Covered	T197,T313,T315
1	1	Covered	T197,T313,T315

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T197,T313,T315

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T197,T52,T313
0	Covered	T197,T313,T315

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T197,T52,T313
0	Covered	T197,T313,T315

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	542445574	534351411	0	0
CheckNGreaterZero_A	1024	1024	0	0
GntImpliesReady_A	542445574	3190	0	0
GntImpliesValid_A	542445574	3190	0	0
GrantKnown_A	542445574	534351411	0	0
IdxKnown_A	542445574	534351411	0	0
IndexIsCorrect_A	542445574	3190	0	0
NoReadyValidNoGrant_A	542445574	0	0	0
Priority_A	542445574	3190	0	0
ReadyAndValidImplyGrant_A	542445574	3190	0	0
ReqAndReadyImplyGrant_A	542445574	3190	0	0
ReqImpliesValid_A	542445574	3190	0	0
ValidKnown_A	542445574	534351411	0	0
gen_data_port_assertion.DataFlow_A	542445574	3190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	534351411	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T21	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	3190	0	0
T197	84647	1063	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1064	0	0
T315	0	1063	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	3190	0	0
T197	84647	1063	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1064	0	0
T315	0	1063	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	534351411	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	534351411	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	3190	0	0
T197	84647	1063	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1064	0	0
T315	0	1063	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	3190	0	0
T197	84647	1063	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1064	0	0
T315	0	1063	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	3190	0	0
T197	84647	1063	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1064	0	0
T315	0	1063	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	3190	0	0
T197	84647	1063	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1064	0	0
T315	0	1063	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	3190	0	0
T197	84647	1063	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1064	0	0
T315	0	1063	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	534351411	0	0
T1	197955	197904	0	0
T2	231310	231106	0	0
T3	714353	714295	0	0
T4	101890	101835	0	0
T5	537765	537495	0	0
T6	118847	118835	0	0
T7	435656	435317	0	0
T21	155692	155634	0	0
T86	157831	157773	0	0
T87	506792	506730	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542445574	3190	0	0
T197	84647	1063	0	0
T258	298512	0	0	0
T297	110314	0	0	0
T298	97941	0	0	0
T313	0	1064	0	0
T315	0	1063	0	0
T360	187790	0	0	0
T415	285084	0	0	0
T416	248293	0	0	0
T417	254395	0	0	0
T418	388468	0	0	0
T419	242501	0	0	0