Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3932359	1			T85	19457		T86	16		T87	1991
values[2]	775103	1			T85	4756		T86	16		T87	538
values[3]	113283	1			T85	470		T86	16		T87	18
values[4]	62645	1			T85	301		T86	16		T124	115
values[5]	42402	1			T85	218		T86	16		T124	89
values[6]	31474	1			T85	184		T86	16		T124	99
values[7]	25256	1			T85	208		T86	16		T124	108
values[8]	21218	1			T85	208		T86	16		T124	83
values[9]	18561	1			T85	203		T86	16		T124	93
values[10]	16653	1			T85	157		T86	16		T124	84
values[11]	15666	1			T85	160		T86	16		T124	119
values[12]	14801	1			T85	171		T86	16		T124	119
values[13]	14027	1			T85	179		T86	16		T124	95
values[14]	13680	1			T85	174		T86	16		T124	104
values[15]	13102	1			T85	154		T86	16		T124	84
values[16]	12899	1			T85	154		T86	16		T124	103
values[17]	12177	1			T85	97		T86	16		T124	79
values[18]	11889	1			T85	88		T86	16		T124	81
values[19]	11495	1			T85	100		T86	16		T124	88
values[20]	11243	1			T85	106		T86	17		T124	118
values[21]	10446	1			T85	123		T86	16		T124	102
values[22]	9987	1			T85	112		T86	16		T124	53
values[23]	9969	1			T85	119		T86	16		T124	62
values[24]	9415	1			T85	98		T86	16		T124	78
values[25]	9110	1			T85	110		T86	16		T124	61
values[26]	8623	1			T85	93		T86	16		T124	49
values[27]	8571	1			T85	88		T86	16		T124	63
values[28]	7827	1			T85	97		T86	16		T124	42
values[29]	7483	1			T85	78		T86	16		T124	47
values[30]	7029	1			T85	92		T86	17		T124	39
values[31]	6471	1			T85	75		T86	16		T124	31
values[32]	6095	1			T85	82		T86	16		T124	25
values[33]	5546	1			T85	83		T86	16		T124	22
values[34]	5398	1			T85	61		T86	16		T124	19
values[35]	4968	1			T85	42		T86	16		T124	12
values[36]	4614	1			T85	38		T86	16		T124	27
values[37]	4387	1			T85	41		T86	16		T124	16
values[38]	4245	1			T85	35		T86	16		T124	12
values[39]	4003	1			T85	26		T86	16		T124	13
values[40]	3755	1			T85	26		T86	16		T124	9
values[41]	3688	1			T85	29		T86	16		T124	13
values[42]	3569	1			T85	26		T86	16		T124	9
values[43]	3458	1			T85	23		T86	16		T124	8
values[44]	3421	1			T85	19		T86	16		T124	7
values[45]	3349	1			T85	22		T86	16		T124	8
values[46]	3233	1			T85	19		T86	17		T124	8
values[47]	3219	1			T85	29		T86	16		T124	8
values[48]	3200	1			T85	28		T86	16		T124	28
values[49]	3163	1			T85	15		T86	16		T124	11
values[50]	3077	1			T85	24		T86	17		T124	3
values[51]	3072	1			T85	19		T86	16		T124	8
values[52]	3007	1			T85	13		T86	16		T124	6
values[53]	2867	1			T85	17		T86	18		T124	3
values[54]	2887	1			T85	23		T86	16		T124	7
values[55]	2871	1			T85	9		T86	17		T124	2
values[56]	2763	1			T85	13		T86	16		T124	6
values[57]	2766	1			T85	15		T86	16		T124	2
values[58]	2691	1			T85	11		T86	16		T124	7
values[59]	2683	1			T85	11		T86	17		T124	7
values[60]	2684	1			T85	12		T86	16		T124	1
values[61]	2905	1			T85	7		T86	16		T124	6
values[62]	4345	1			T85	8		T86	16		T124	2
values[63]	11847	1			T85	28		T86	18		T124	3
values[64]	243497	1			T85	400		T86	3047		T124	1

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	5050091	1			T85	25576		T86	2225		T87	2000
values[2]	850563	1			T85	4719		T86	676		T87	539
values[3]	87487	1			T85	133		T86	202		T87	99
values[4]	14843	1			T85	18		T86	48		T87	6
values[5]	5686	1			T85	10		T86	15		T87	2
values[6]	3628	1			T85	13		T86	8		T87	1
values[7]	2882	1			T85	8		T86	5		T554	5
values[8]	2368	1			T85	14		T86	3		T554	4
values[9]	1854	1			T85	12		T86	3		T554	2
values[10]	1672	1			T85	9		T86	3		T554	1
values[11]	1550	1			T85	8		T86	3		T554	1
values[12]	1493	1			T85	11		T86	3		T554	1
values[13]	1351	1			T85	17		T86	3		T554	1
values[14]	1204	1			T85	10		T86	3		T554	1
values[15]	1107	1			T85	17		T86	3		T554	1
values[16]	1067	1			T85	8		T86	3		T554	1
values[17]	1110	1			T85	10		T86	3		T554	1
values[18]	1043	1			T85	11		T86	3		T554	1
values[19]	1070	1			T85	11		T86	3		T554	1
values[20]	1020	1			T85	13		T86	3		T554	1
values[21]	1007	1			T85	13		T86	3		T554	1
values[22]	835	1			T85	12		T86	3		T554	1
values[23]	830	1			T85	10		T86	3		T554	1
values[24]	751	1			T85	10		T86	3		T554	1
values[25]	713	1			T85	9		T86	3		T554	1
values[26]	711	1			T85	10		T86	4		T554	1
values[27]	768	1			T85	14		T86	3		T554	1
values[28]	726	1			T85	10		T86	3		T554	2
values[29]	664	1			T85	9		T86	3		T554	1
values[30]	689	1			T85	10		T86	3		T554	1
values[31]	680	1			T85	13		T86	3		T554	1
values[32]	589	1			T85	10		T86	3		T554	1
values[33]	625	1			T85	12		T86	3		T554	1
values[34]	615	1			T85	10		T86	3		T554	1
values[35]	575	1			T85	7		T86	4		T554	1
values[36]	565	1			T85	10		T86	3		T554	1
values[37]	498	1			T85	8		T86	3		T554	1
values[38]	544	1			T85	7		T86	3		T554	1
values[39]	561	1			T85	20		T86	3		T554	1
values[40]	523	1			T85	11		T86	3		T554	1
values[41]	534	1			T85	12		T86	3		T554	1
values[42]	485	1			T85	11		T86	3		T554	1
values[43]	474	1			T85	18		T86	3		T554	1
values[44]	439	1			T85	9		T86	3		T554	1
values[45]	439	1			T85	8		T86	3		T554	1
values[46]	470	1			T85	11		T86	3		T554	1
values[47]	446	1			T85	8		T86	3		T554	1
values[48]	406	1			T85	9		T86	3		T554	1
values[49]	406	1			T85	14		T86	3		T554	1
values[50]	436	1			T85	12		T86	3		T554	1
values[51]	457	1			T85	15		T86	3		T554	1
values[52]	426	1			T85	9		T86	3		T554	1
values[53]	409	1			T85	10		T86	3		T554	1
values[54]	423	1			T85	10		T86	3		T554	1
values[55]	402	1			T85	8		T86	3		T554	1
values[56]	363	1			T85	9		T86	3		T554	1
values[57]	404	1			T85	10		T86	3		T554	1
values[58]	392	1			T85	11		T86	3		T554	1
values[59]	412	1			T85	8		T86	3		T554	1
values[60]	419	1			T85	9		T86	3		T554	1
values[61]	454	1			T85	7		T86	3		T554	1
values[62]	743	1			T85	7		T86	3		T554	1
values[63]	2754	1			T85	27		T86	3		T554	1
values[64]	28537	1			T85	569		T86	575		T554	235

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	624408	1			T85	3264		T86	16		T87	20
values[2]	2751639	1			T85	16455		T86	16		T87	954
values[3]	1262867	1			T85	4248		T86	16		T87	1541
values[4]	160338	1			T85	395		T86	16		T87	24
values[5]	83780	1			T85	222		T86	16		T124	82
values[6]	54959	1			T85	182		T86	16		T124	97
values[7]	39890	1			T85	164		T86	16		T124	74
values[8]	31602	1			T85	218		T86	16		T124	105
values[9]	26415	1			T85	224		T86	16		T124	80
values[10]	22906	1			T85	192		T86	16		T124	95
values[11]	20920	1			T85	197		T86	16		T124	91
values[12]	18564	1			T85	141		T86	16		T124	82
values[13]	17615	1			T85	152		T86	16		T124	80
values[14]	16779	1			T85	167		T86	16		T124	74
values[15]	15811	1			T85	139		T86	17		T124	71
values[16]	15380	1			T85	187		T86	16		T124	86
values[17]	14411	1			T85	184		T86	16		T124	101
values[18]	14117	1			T85	231		T86	16		T124	97
values[19]	13933	1			T85	147		T86	16		T124	114
values[20]	12916	1			T85	151		T86	16		T124	98
values[21]	12298	1			T85	167		T86	16		T124	67
values[22]	11560	1			T85	128		T86	16		T124	74
values[23]	11213	1			T85	103		T86	16		T124	86
values[24]	11116	1			T85	109		T86	16		T124	71
values[25]	10788	1			T85	108		T86	16		T124	53
values[26]	10153	1			T85	100		T86	16		T124	54
values[27]	9853	1			T85	68		T86	16		T124	65
values[28]	9229	1			T85	61		T86	16		T124	59
values[29]	8662	1			T85	55		T86	16		T124	48
values[30]	8013	1			T85	60		T86	16		T124	42
values[31]	7385	1			T85	72		T86	16		T124	40
values[32]	6658	1			T85	59		T86	16		T124	27
values[33]	6330	1			T85	44		T86	16		T124	21
values[34]	5885	1			T85	45		T86	16		T124	11
values[35]	5514	1			T85	32		T86	16		T124	20
values[36]	5199	1			T85	29		T86	16		T124	15
values[37]	4840	1			T85	22		T86	18		T124	20
values[38]	4686	1			T85	22		T86	16		T124	14
values[39]	4415	1			T85	11		T86	16		T124	7
values[40]	4192	1			T85	12		T86	16		T124	9
values[41]	4025	1			T85	10		T86	16		T124	4
values[42]	3879	1			T85	14		T86	16		T124	9
values[43]	3861	1			T85	8		T86	16		T124	9
values[44]	3756	1			T85	17		T86	16		T124	9
values[45]	3589	1			T85	10		T86	16		T124	4
values[46]	3418	1			T85	19		T86	16		T124	11
values[47]	3566	1			T85	13		T86	17		T124	2
values[48]	3510	1			T85	12		T86	17		T124	4
values[49]	3516	1			T85	8		T86	16		T124	3
values[50]	3398	1			T85	23		T86	16		T124	4
values[51]	3400	1			T85	11		T86	16		T124	3
values[52]	3416	1			T85	7		T86	16		T124	4
values[53]	3279	1			T85	8		T86	16		T124	4
values[54]	3247	1			T85	25		T86	16		T124	2
values[55]	3232	1			T85	14		T86	17		T124	2
values[56]	3180	1			T85	7		T86	16		T554	13
values[57]	3052	1			T85	7		T86	16		T554	13
values[58]	2913	1			T85	4		T86	16		T554	13
values[59]	2742	1			T85	3		T86	16		T554	13
values[60]	2776	1			T85	9		T86	16		T554	13
values[61]	2925	1			T85	11		T86	16		T554	13
values[62]	4011	1			T85	10		T86	16		T554	13
values[63]	9856	1			T85	4		T86	18		T554	31
values[64]	228567	1			T85	231		T86	2933		T554	2208