Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2107711	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40655804

1

T1

17188

T2

8113

T3

7336

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29669037	1			T1	13113		T2	3934		T3	1944
values[0x0]	11596896	1			T1	4075		T2	4179		T3	5392
values[0x1]	1497582	1			T1	3728		T2	427		T3	276

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	744115	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42019400

1

T1

20916

T2

8540

T3

7612

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20068451	1			T1	10458		T2	4270		T3	3807
valid_sources[0x01]	20067613	1			T1	10458		T2	4270		T3	3805
valid_sources[0x02]	42909	1			T198	1		T407	258		T411	121
valid_sources[0x03]	42446	1			T75	1		T88	1		T198	1
valid_sources[0x04]	42655	1			T75	1		T88	1		T407	276
valid_sources[0x05]	42738	1			T88	2		T57	39		T407	238
valid_sources[0x06]	42056	1			T75	1		T88	2		T407	241
valid_sources[0x07]	42755	1			T407	240		T411	136		T142	837
valid_sources[0x08]	41872	1			T75	3		T198	2		T407	236
valid_sources[0x09]	41168	1			T88	1		T407	254		T411	152
valid_sources[0x0a]	42513	1			T198	2		T407	243		T411	156
valid_sources[0x0b]	41510	1			T88	3		T52	7		T407	234
valid_sources[0x0c]	42250	1			T88	1		T198	1		T407	264
valid_sources[0x0d]	51858	1			T75	1		T88	1		T407	241
valid_sources[0x0e]	42104	1			T88	1		T407	263		T411	121
valid_sources[0x0f]	42358	1			T75	1		T88	2		T407	229
valid_sources[0x10]	41435	1			T198	2		T407	245		T411	117
valid_sources[0x11]	41926	1			T198	1		T407	284		T411	124
valid_sources[0x12]	41947	1			T75	2		T407	251		T411	151
valid_sources[0x13]	41414	1			T407	265		T411	138		T142	735
valid_sources[0x14]	42744	1			T198	1		T407	237		T411	129
valid_sources[0x15]	42421	1			T198	1		T407	240		T411	108
valid_sources[0x16]	41935	1			T75	1		T407	252		T411	126
valid_sources[0x17]	42411	1			T88	1		T198	1		T407	220
valid_sources[0x18]	42246	1			T75	2		T51	18		T407	223
valid_sources[0x19]	41705	1			T407	254		T411	105		T142	727
valid_sources[0x1a]	41918	1			T75	1		T88	1		T198	1
valid_sources[0x1b]	42050	1			T75	1		T407	249		T411	146
valid_sources[0x1c]	42049	1			T88	3		T407	278		T411	125
valid_sources[0x1d]	41826	1			T88	1		T198	2		T407	255
valid_sources[0x1e]	42202	1			T52	25		T198	1		T407	257
valid_sources[0x1f]	42465	1			T75	2		T407	237		T411	134
valid_sources[0x20]	42470	1			T407	258		T411	118		T142	804

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28845337

1

T1

13113

T2

3934

T3

1944

values[0x0]

all_enables

biggest_size

11534129

1

T1

4075

T2

4179

T3

5392

values[0x1]

all_enables

biggest_size

276338

1

T75

18

T88

25

T51

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3072033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

486802

1

T85

134

T86

544

T87

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1205628	1			T85	633		T86	1387		T87	37
values[0x0]	1149852	1			T85	100		T86	1310		T87	8
values[0x1]	1203355	1			T85	637		T86	1368		T87	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2377294	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1181541

1

T85

527

T86

1324

T87

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55466	1			T85	34		T86	60		T87	1
valid_sources[0x01]	55384	1			T85	14		T86	58		T87	1
valid_sources[0x02]	55866	1			T85	29		T86	67		T87	2
valid_sources[0x03]	55688	1			T85	22		T86	66		T87	2
valid_sources[0x04]	56000	1			T85	34		T86	65		T87	1
valid_sources[0x05]	55198	1			T85	19		T86	61		T87	2
valid_sources[0x06]	56240	1			T85	10		T86	71		T87	1
valid_sources[0x07]	55283	1			T85	28		T86	58		T87	1
valid_sources[0x08]	57504	1			T85	26		T86	50		T87	3
valid_sources[0x09]	55892	1			T85	19		T86	75		T87	5
valid_sources[0x0a]	55461	1			T85	16		T86	65		T87	5
valid_sources[0x0b]	55421	1			T85	41		T86	65		T87	1
valid_sources[0x0c]	54035	1			T85	17		T86	62		T87	4
valid_sources[0x0d]	56092	1			T85	19		T86	59		T87	2
valid_sources[0x0e]	55996	1			T85	21		T86	59		T87	1
valid_sources[0x0f]	55273	1			T85	22		T86	70		T87	2
valid_sources[0x10]	54633	1			T85	18		T86	65		T124	11
valid_sources[0x11]	54575	1			T85	22		T86	64		T87	1
valid_sources[0x12]	56483	1			T85	25		T86	60		T124	20
valid_sources[0x13]	56309	1			T85	14		T86	64		T87	2
valid_sources[0x14]	56013	1			T85	26		T86	63		T87	1
valid_sources[0x15]	55082	1			T85	29		T86	63		T87	1
valid_sources[0x16]	54702	1			T85	25		T86	69		T87	2
valid_sources[0x17]	54933	1			T85	8		T86	68		T87	1
valid_sources[0x18]	55743	1			T85	20		T86	62		T87	1
valid_sources[0x19]	54444	1			T85	11		T86	56		T87	1
valid_sources[0x1a]	55368	1			T85	20		T86	64		T87	1
valid_sources[0x1b]	55736	1			T85	26		T86	53		T87	1
valid_sources[0x1c]	54629	1			T85	21		T86	62		T87	2
valid_sources[0x1d]	54628	1			T85	29		T86	61		T124	15
valid_sources[0x1e]	55637	1			T85	40		T86	60		T87	1
valid_sources[0x1f]	56883	1			T85	14		T86	65		T87	4
valid_sources[0x20]	55774	1			T85	20		T86	70		T87	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51220

1

T85

48

T86

51

T87

1

values[0x0]

all_enables

biggest_size

384896

1

T85

45

T86

431

T87

2

values[0x1]

all_enables

biggest_size

50686

1

T85

41

T86

62

T87

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3280011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

534226

1

T85

175

T86

578

T87

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1305974	1			T85	594		T86	1290		T87	58
values[0x0]	1201537	1			T85	133		T86	1283		T87	9
values[0x1]	1306726	1			T85	624		T86	1351		T87	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2516757	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1297480

1

T85

549

T86

1336

T87

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	60829	1			T85	33		T86	54		T124	24
valid_sources[0x01]	59565	1			T85	15		T86	67		T87	3
valid_sources[0x02]	60470	1			T85	20		T86	58		T87	1
valid_sources[0x03]	59747	1			T85	29		T86	62		T124	20
valid_sources[0x04]	59701	1			T85	32		T86	60		T87	1
valid_sources[0x05]	60360	1			T85	29		T86	85		T87	2
valid_sources[0x06]	58921	1			T85	19		T86	66		T87	2
valid_sources[0x07]	59013	1			T85	24		T86	35		T87	2
valid_sources[0x08]	60108	1			T85	24		T86	68		T87	2
valid_sources[0x09]	58744	1			T85	21		T86	47		T87	3
valid_sources[0x0a]	60000	1			T85	8		T86	52		T124	17
valid_sources[0x0b]	60100	1			T85	16		T86	65		T87	2
valid_sources[0x0c]	58755	1			T85	17		T86	41		T87	4
valid_sources[0x0d]	58364	1			T85	22		T86	60		T87	2
valid_sources[0x0e]	59585	1			T85	25		T86	60		T87	2
valid_sources[0x0f]	59633	1			T85	18		T86	57		T124	17
valid_sources[0x10]	59507	1			T85	16		T86	65		T87	2
valid_sources[0x11]	60660	1			T85	18		T86	68		T87	3
valid_sources[0x12]	59505	1			T85	27		T86	77		T87	1
valid_sources[0x13]	59396	1			T85	15		T86	61		T87	3
valid_sources[0x14]	59626	1			T85	33		T86	73		T87	2
valid_sources[0x15]	59385	1			T85	35		T86	80		T124	23
valid_sources[0x16]	58942	1			T85	21		T86	57		T87	1
valid_sources[0x17]	59360	1			T85	20		T86	74		T124	19
valid_sources[0x18]	59891	1			T85	17		T86	78		T87	1
valid_sources[0x19]	59145	1			T85	27		T86	53		T87	2
valid_sources[0x1a]	59564	1			T85	16		T86	68		T124	8
valid_sources[0x1b]	60283	1			T85	26		T86	55		T87	3
valid_sources[0x1c]	58825	1			T85	27		T86	60		T87	2
valid_sources[0x1d]	59446	1			T85	18		T86	57		T87	1
valid_sources[0x1e]	59905	1			T85	29		T86	70		T87	3
valid_sources[0x1f]	58409	1			T85	16		T86	64		T87	1
valid_sources[0x20]	59278	1			T85	22		T86	67		T87	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

56056

1

T85

52

T86

59

T87

9

values[0x0]

all_enables

biggest_size

422163

1

T85

59

T86

458

T87

4

values[0x1]

all_enables

biggest_size

56007

1

T85

64

T86

61

T87

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3101571	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

491581

1

T85

122

T86

545

T87

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1215896	1			T85	582		T86	1300		T87	57
values[0x0]	1160767	1			T85	97		T86	1294		T87	5
values[0x1]	1216489	1			T85	590		T86	1355		T87	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2401699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1191453

1

T85

481

T86

1292

T87

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56503	1			T85	30		T86	57		T87	1
valid_sources[0x01]	55864	1			T85	17		T86	63		T87	2
valid_sources[0x02]	56990	1			T85	22		T86	69		T87	2
valid_sources[0x03]	56025	1			T85	20		T86	68		T87	1
valid_sources[0x04]	56608	1			T85	18		T86	62		T87	1
valid_sources[0x05]	55876	1			T85	19		T86	66		T87	1
valid_sources[0x06]	56059	1			T85	18		T86	48		T124	15
valid_sources[0x07]	55350	1			T85	20		T86	54		T87	2
valid_sources[0x08]	56299	1			T85	19		T86	70		T87	1
valid_sources[0x09]	56700	1			T85	30		T86	61		T87	3
valid_sources[0x0a]	55037	1			T85	17		T86	62		T87	5
valid_sources[0x0b]	56104	1			T85	20		T86	66		T87	4
valid_sources[0x0c]	56014	1			T85	20		T86	53		T87	2
valid_sources[0x0d]	56208	1			T85	22		T86	51		T124	31
valid_sources[0x0e]	56768	1			T85	17		T86	50		T87	2
valid_sources[0x0f]	56251	1			T85	18		T86	67		T87	1
valid_sources[0x10]	56533	1			T85	20		T86	51		T87	2
valid_sources[0x11]	55995	1			T85	19		T86	42		T87	2
valid_sources[0x12]	55941	1			T85	19		T86	50		T124	12
valid_sources[0x13]	56296	1			T85	18		T86	69		T87	2
valid_sources[0x14]	56703	1			T85	22		T86	58		T87	2
valid_sources[0x15]	55351	1			T85	25		T86	69		T87	1
valid_sources[0x16]	55723	1			T85	20		T86	57		T124	14
valid_sources[0x17]	55994	1			T85	17		T86	81		T87	1
valid_sources[0x18]	56207	1			T85	15		T86	58		T87	3
valid_sources[0x19]	55813	1			T85	24		T86	71		T87	2
valid_sources[0x1a]	56485	1			T85	18		T86	62		T87	1
valid_sources[0x1b]	55467	1			T85	20		T86	68		T87	1
valid_sources[0x1c]	55898	1			T85	23		T86	65		T87	1
valid_sources[0x1d]	56004	1			T85	13		T86	64		T87	2
valid_sources[0x1e]	55734	1			T85	13		T86	68		T87	3
valid_sources[0x1f]	56155	1			T85	22		T86	57		T87	3
valid_sources[0x20]	55559	1			T85	25		T86	66		T124	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51146

1

T85

44

T86

54

T87

4

values[0x0]

all_enables

biggest_size

388727

1

T85

31

T86

433

T87

3

values[0x1]

all_enables

biggest_size

51708

1

T85

47

T86

58

T87

3