Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T42,T145,T5	Yes	T42,T145,T5	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T42,T145,T5	Yes	T42,T145,T5	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	INPUT
tl_i.a_valid	Yes	Yes	T42,T145,T152	Yes	T42,T145,T152	INPUT
tl_o.a_ready	Yes	Yes	T42,T145,T152	Yes	T42,T145,T152	OUTPUT
tl_o.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T42,T145,T5	Yes	T42,T145,T5	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T42,T145,T152	Yes	T42,T145,T152	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T42,T145,T152	Yes	T42,T145,T152	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T254,*T255	Yes	T76,T254,T255	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T42,*T145,*T5	Yes	T42,T145,T5	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T42,T145,T152	Yes	T42,T145,T152	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T65,T762	Yes	T152,T65,T762	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T89,T156,T90	Yes	T89,T156,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T89,T156,T90	Yes	T89,T156,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T65,T762	Yes	T152,T65,T762	OUTPUT
cio_rx_i	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T42,T145,T5	Yes	T42,T145,T5	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T145,T5,T295	Yes	T145,T5,T295	OUTPUT
intr_tx_empty_o	Yes	Yes	T145,T5,T295	Yes	T145,T5,T295	OUTPUT
intr_rx_watermark_o	Yes	Yes	T145,T5,T295	Yes	T145,T5,T295	OUTPUT
intr_tx_done_o	Yes	Yes	T145,T5,T295	Yes	T145,T5,T295	OUTPUT
intr_rx_overflow_o	Yes	Yes	T145,T5,T295	Yes	T145,T5,T295	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_break_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_timeout_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	INPUT
tl_i.a_valid	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	INPUT
tl_o.a_ready	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	OUTPUT
tl_o.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T254,*T255	Yes	T76,T254,T255	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T42,*T43,*T6	Yes	T42,T43,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T65,T762	Yes	T152,T65,T762	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T89,T156,T90	Yes	T89,T156,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T89,T156,T90	Yes	T89,T156,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T65,T762	Yes	T152,T65,T762	OUTPUT
cio_rx_i	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T118,T215,T216	Yes	T118,T215,T216	OUTPUT
intr_tx_empty_o	Yes	Yes	T118,T215,T216	Yes	T118,T215,T216	OUTPUT
intr_rx_watermark_o	Yes	Yes	T118,T215,T216	Yes	T118,T215,T216	OUTPUT
intr_tx_done_o	Yes	Yes	T118,T359,T215	Yes	T118,T359,T215	OUTPUT
intr_rx_overflow_o	Yes	Yes	T118,T359,T215	Yes	T118,T359,T215	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_break_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_timeout_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	INPUT
tl_i.a_valid	Yes	Yes	T152,T5,T65	Yes	T152,T5,T65	INPUT
tl_o.a_ready	Yes	Yes	T152,T5,T65	Yes	T152,T5,T65	OUTPUT
tl_o.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T152,T5,T209	Yes	T152,T5,T65	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T152,T5,T209	Yes	T152,T5,T65	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T209,*T210	Yes	T5,T209,T210	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T152,T5,T65	Yes	T152,T5,T65	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T65,T89	Yes	T152,T65,T89	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T89,T90,T157	Yes	T89,T90,T157	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T89,T90,T157	Yes	T89,T90,T157	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T65,T89	Yes	T152,T65,T89	OUTPUT
cio_rx_i	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	INPUT
cio_tx_o	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_break_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_timeout_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	INPUT
tl_i.a_valid	Yes	Yes	T145,T152,T65	Yes	T145,T152,T65	INPUT
tl_o.a_ready	Yes	Yes	T145,T152,T65	Yes	T145,T152,T65	OUTPUT
tl_o.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T145,T152,T295	Yes	T145,T152,T65	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T145,T152,T295	Yes	T145,T152,T65	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T145,*T295,*T355	Yes	T145,T295,T355	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T145,T152,T65	Yes	T145,T152,T65	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T65,T89	Yes	T152,T65,T89	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T89,T90,T91	Yes	T89,T90,T91	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T89,T90,T91	Yes	T89,T90,T91	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T65,T89	Yes	T152,T65,T89	OUTPUT
cio_rx_i	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	INPUT
cio_tx_o	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	OUTPUT
intr_tx_empty_o	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	OUTPUT
intr_rx_watermark_o	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	OUTPUT
intr_tx_done_o	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	OUTPUT
intr_rx_overflow_o	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_break_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_timeout_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	INPUT
tl_i.a_valid	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	INPUT
tl_o.a_ready	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	OUTPUT
tl_o.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T344,*T294	Yes	T1,T344,T294	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T65,T89	Yes	T152,T65,T89	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T89,T156,T90	Yes	T89,T156,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T89,T156,T90	Yes	T89,T156,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T65,T89	Yes	T152,T65,T89	OUTPUT
cio_rx_i	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	INPUT
cio_tx_o	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	OUTPUT
intr_tx_empty_o	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	OUTPUT
intr_rx_watermark_o	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	OUTPUT
intr_tx_done_o	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	OUTPUT
intr_rx_overflow_o	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_break_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_timeout_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T347,T342,T348	Yes	T347,T342,T348	OUTPUT

*Tests covering at least one bit in the range