Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T71,T217,T218	Yes	T71,T217,T218	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T71,T217,T240	Yes	T71,T217,T240	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T57,T85,T86	Yes	T57,T85,T86	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T70,T71,T152	Yes	T70,T71,T152	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T254	Yes	T75,T76,T254	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T75,T76,T254	Yes	T75,T76,T254	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T75,T76,T149	Yes	T75,T76,T149	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T75,T76,T254	Yes	T75,T76,T254	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T75,T76,T149	Yes	T75,T76,T149	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T254	Yes	T76,T77,T254	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T76,T77,T254	Yes	T76,T77,T254	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T76,T77,T254	Yes	T76,T77,T254	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T76,T77,T254	Yes	T76,T77,T254	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T76,T77,T254	Yes	T76,T77,T254	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T254	Yes	T76,T77,T254	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T76,T77,T254	Yes	T76,T77,T254	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T76,T77,T254	Yes	T76,T77,T254	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T254	Yes	T76,T77,T254	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T254	Yes	T76,T77,T254	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T3,T4,T28	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T76,T77,T254	Yes	T76,T77,T254	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T65,T51,T52	Yes	T65,T51,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T276,T65,T427	Yes	T276,T65,T427	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T276,T65,T427	Yes	T276,T65,T427	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T65,T51,T52	Yes	T65,T51,T52	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T276,T65,T427	Yes	T276,T65,T427	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T276,T65,T427	Yes	T276,T65,T427	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T276,T65,T427	Yes	T276,T65,T427	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T85,T124,T428	Yes	T85,T124,T428	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T276,T427,T429	Yes	T276,T427,T429	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T52,T57	Yes	T65,T51,T52	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T276,T427,T429	Yes	T276,T65,T427	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T86,T87	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T87,T124	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T276,*T430,*T51	Yes	T276,T427,T429	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T276,T65,T427	Yes	T276,T65,T427	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T70,T240,T218	Yes	T70,T240,T218	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T254	Yes	T75,T76,T77	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T11,T194,T195	Yes	T11,T194,T195	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T206,T10,T153	Yes	T206,T10,T153	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T206,T10	Yes	T152,T206,T65	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T206,T10,T153	Yes	T206,T10,T153	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T206,*T10,*T153	Yes	T206,T10,T153	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T206,T65,T153	Yes	T206,T65,T153	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T206,T65,T153	Yes	T206,T65,T153	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T206,T65,T153	Yes	T206,T65,T153	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T206,T65,T153	Yes	T206,T65,T153	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T206,T65,T153	Yes	T206,T65,T153	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T206,T65,T153	Yes	T206,T65,T153	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T206,T65,T153	Yes	T206,T65,T153	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T206,T65,T153	Yes	T206,T65,T153	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T206,T153,T269	Yes	T206,T153,T269	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T206,T153,T269	Yes	T206,T65,T153	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T206,T153,T269	Yes	T206,T153,T269	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T206,*T153,*T269	Yes	T206,T153,T269	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T206,T65,T153	Yes	T206,T65,T153	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T245,T206,T65	Yes	T245,T206,T65	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T245,T206,T65	Yes	T245,T206,T65	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T245,T206,T65	Yes	T245,T206,T65	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T245,T206,T65	Yes	T245,T206,T65	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T206,T65,T14	Yes	T206,T65,T14	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T245,T206,T65	Yes	T245,T206,T65	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T245,T206,T65	Yes	T245,T206,T65	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T245,T206,T65	Yes	T245,T206,T65	INPUT
tl_usbdev_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T245,T206,T14	Yes	T245,T206,T14	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T245,T206,T14	Yes	T245,T206,T14	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T245,T206,T65	Yes	T245,T206,T14	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T245,*T206,*T65	Yes	T245,T206,T14	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T245,T206,T65	Yes	T245,T206,T65	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T57,T85,T87	Yes	T57,T85,T87	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T57,T85,T86	Yes	T57,T85,T86	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T57,T85,T87	Yes	T57,T85,T87	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T57,T85,T87	Yes	T57,T85,T87	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T444,T756,T757	Yes	T444,T756,T757	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_hmac_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_hmac_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T42,*T43,*T6	Yes	T42,T43,T6	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_kmac_o.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T95,T459,T123	Yes	T95,T459,T123	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T95,T96,T459	Yes	T95,T96,T459	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T95,T96,T459	Yes	T95,T96,T459	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T95,T459,T123	Yes	T95,T459,T123	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T95,T96,T459	Yes	T95,T96,T459	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T95,T459,T460	Yes	T95,T459,T460	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T95,T96,T459	Yes	T95,T96,T459	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T95,T96,T459	Yes	T95,T96,T459	INPUT
tl_kmac_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T95,T96,T459	Yes	T95,T96,T459	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T95,T96,T459	Yes	T95,T96,T459	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T95,T96,T459	Yes	T95,T96,T459	INPUT
tl_kmac_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T95,*T96,*T459	Yes	T95,T96,T459	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T95,T96,T459	Yes	T95,T96,T459	INPUT
tl_aes_o.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T394,T395,T65	Yes	T394,T395,T65	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T394,T395,T65	Yes	T394,T395,T65	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T394,T395,T749	Yes	T394,T395,T749	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T394,T395,T65	Yes	T394,T395,T65	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T394,T395,T749	Yes	T394,T395,T749	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T394,T395,T749	Yes	T394,T395,T749	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T394,T395,T749	Yes	T394,T395,T749	INPUT
tl_aes_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T87,T124	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T394,T395,T749	Yes	T394,T395,T749	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T394,T395,T256	Yes	T394,T395,T256	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T394,T395,T749	Yes	T394,T395,T749	INPUT
tl_aes_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T87,T124	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T87,T124	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T394,*T395,*T749	Yes	T394,T395,T749	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T394,T395,T749	Yes	T394,T395,T749	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T94,T4	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T94,*T121,*T123	Yes	T94,T42,T121	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T57,*T85,*T86	Yes	T57,T85,T86	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T94,T4	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T86	Yes	T57,T85,T86	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T94,*T121,*T123	Yes	T94,T121,T123	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T94,T4	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T3,T94,T4	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T94,*T121,*T123	Yes	T94,T121,T123	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T3,T94,T4	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	INPUT
tl_edn1_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	INPUT
tl_edn1_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T94,*T121,*T123	Yes	T94,T121,T123	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T94,T121,T123	Yes	T94,T121,T123	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_otbn_o.d_ready	Yes	Yes	T3,T94,T4	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T75,*T88,*T198	Yes	T75,T88,T198	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	INPUT
tl_otbn_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	INPUT
tl_otbn_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T75,*T88,*T198	Yes	T75,T88,T198	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T94,*T42,*T121	Yes	T94,T42,T121	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T94,T42,T121	Yes	T94,T42,T121	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T42,T96,T123	Yes	T42,T96,T123	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T96,T123	Yes	T42,T96,T123	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T42,T96,T123	Yes	T42,T96,T123	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T96,T123,T43	Yes	T96,T123,T43	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T42,T96,T123	Yes	T42,T96,T123	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T42,T96,T123	Yes	T42,T96,T123	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T42,T96,T123	Yes	T42,T96,T123	INPUT
tl_keymgr_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T96,T123,T219	Yes	T96,T123,T219	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T96,T123	Yes	T42,T96,T123	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T42,T96,T123	Yes	T42,T96,T123	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T86	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T42,*T96,*T123	Yes	T42,T96,T123	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T42,T96,T123	Yes	T42,T96,T123	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T76,*T51,*T255	Yes	T76,T51,T255	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T51,T52,T57	Yes	T51,T52,T57	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T94,T4	Yes	T2,T94,T4	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T94,T4	Yes	T2,T94,T4	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T76,T51,T255	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T455,*T85,*T87	Yes	T455,T85,T87	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T174,T175,T316	Yes	T174,T175,T316	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T40,T41	Yes	T42,T43,T6	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T6,T40,T41	Yes	T42,T43,T6	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T455,T85,T87	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T116,*T173,*T174	Yes	T116,T173,T244	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range