Unified Coverage Report :: Module :: pwrmgr

Module : pwrmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57			99.57

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pwrmgr_aon	99.57			99.57

---

Module Instance : tb.dut.top_earlgrey.u_pwrmgr_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57			99.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57			99.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

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Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pwrmgr

	Total	Covered	Percent
Totals	84	83	98.81
Total Bits	462	460	99.57
Total Bits 0->1	231	230	99.57
Total Bits 1->0	231	230	99.57

Ports	84	83	98.81
Port Bits	462	460	99.57
Port Bits 0->1	231	230	99.57
Port Bits 1->0	231	230	99.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_slow_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_slow_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T3,T28,T125	Yes	T1,T2,T3	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_i.a_address[21:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	INPUT
tl_i.a_valid	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	INPUT
tl_o.a_ready	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	OUTPUT
tl_o.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	OUTPUT
tl_o.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T28,*T42	Yes	T2,T28,T42	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T125,T65,T721	Yes	T125,T65,T721	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T89,T90,T91	Yes	T89,T90,T91	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T89,T90,T91	Yes	T89,T90,T91	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T125,T65,T721	Yes	T125,T65,T721	OUTPUT
pwr_ast_i.main_pok	Yes	Yes	T3,T28,T125	Yes	T1,T2,T3	INPUT
pwr_ast_i.usb_clk_val	Yes	Yes	T2,T3,T28	Yes	T1,T2,T3	INPUT
pwr_ast_i.io_clk_val	Yes	Yes	T2,T3,T28	Yes	T1,T2,T3	INPUT
pwr_ast_i.core_clk_val	Yes	Yes	T2,T3,T28	Yes	T1,T2,T3	INPUT
pwr_ast_i.slow_clk_val	Yes	Yes	T3,T47,T48	Yes	T1,T2,T3	INPUT
pwr_ast_o.usb_clk_en	Yes	Yes	T2,T3,T28	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.io_clk_en	Yes	Yes	T2,T3,T28	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.core_clk_en	Yes	Yes	T2,T3,T28	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.slow_clk_en	No	No		No		OUTPUT
pwr_ast_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T3,T28,T5	OUTPUT
pwr_ast_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T3,T28,T5	OUTPUT
pwr_ast_o.main_pd_n	Yes	Yes	T28,T120,T15	Yes	T28,T120,T15	OUTPUT
pwr_rst_i.rst_sys_src_n[1:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
pwr_rst_i.rst_lc_src_n[1:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
pwr_rst_o.reset_cause[1:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
pwr_rst_o.rstreqs[4:0]	Yes	Yes	T18,T469,T722	Yes	T18,T469,T722	OUTPUT
pwr_rst_o.rst_sys_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	OUTPUT
pwr_rst_o.rst_lc_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	OUTPUT
pwr_clk_o.usb_ip_clk_en	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.io_ip_clk_en	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.main_ip_clk_en	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
pwr_clk_i.usb_status	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
pwr_clk_i.io_status	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
pwr_clk_i.main_status	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
pwr_otp_i.otp_idle	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
pwr_otp_i.otp_done	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_lc_i.lc_idle	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
pwr_lc_i.lc_done	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_flash_i.flash_idle	Yes	Yes	T96,T123,T152	Yes	T96,T123,T152	INPUT
pwr_cpu_i.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
fetch_en_o[3:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
wakeups_i[5:0]	Yes	Yes	T18,T16,T469	Yes	T18,T16,T201	INPUT
rstreqs_i[1:0]	Yes	Yes	T18,T469,T722	Yes	T18,T469,T722	INPUT
ndmreset_req_i	Yes	Yes	T432,T50,T324	Yes	T432,T50,T324	INPUT
strap_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
low_power_o	Yes	Yes	T1,T2,T3	Yes	T2,T3,T28	OUTPUT
rom_ctrl_i.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
rom_ctrl_i.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
sw_rst_req_i[3:0]	Yes	Yes	T96,T123,T152	Yes	T96,T123,T152	INPUT
esc_rst_tx_i.esc_n	Yes	Yes	T4,T70,T71	Yes	T4,T70,T71	INPUT
esc_rst_tx_i.esc_p	Yes	Yes	T4,T70,T71	Yes	T4,T70,T71	INPUT
esc_rst_rx_o.resp_n	Yes	Yes	T4,T70,T71	Yes	T4,T70,T71	OUTPUT
esc_rst_rx_o.resp_p	Yes	Yes	T4,T70,T71	Yes	T4,T70,T71	OUTPUT
intr_wakeup_o	Yes	Yes	T2,T28,T380	Yes	T2,T28,T380	OUTPUT

*Tests covering at least one bit in the range