Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T70,T240,T218	Yes	T70,T240,T218	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T75,*T76,*T254	Yes	T75,T76,T77	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	INPUT
tl_uart0_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T42,T43,T6	Yes	T42,T43,T6	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	INPUT
tl_uart0_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T76,*T254,*T255	Yes	T76,T254,T255	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T42,*T43,*T6	Yes	T42,T43,T6	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T42,T152,T43	Yes	T42,T152,T43	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T152,T5,T65	Yes	T152,T5,T65	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T152,T5,T65	Yes	T152,T5,T65	INPUT
tl_uart1_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T5,T209,T210	Yes	T5,T209,T210	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T5,T209	Yes	T152,T5,T65	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T152,T5,T209	Yes	T152,T5,T65	INPUT
tl_uart1_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T5,*T209,*T210	Yes	T5,T209,T210	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T152,T5,T65	Yes	T152,T5,T65	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T145,T152,T65	Yes	T145,T152,T65	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T145,T152,T65	Yes	T145,T152,T65	INPUT
tl_uart2_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T145,T295,T355	Yes	T145,T295,T355	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T145,T152,T295	Yes	T145,T152,T65	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T145,T152,T295	Yes	T145,T152,T65	INPUT
tl_uart2_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T145,*T295,*T355	Yes	T145,T295,T355	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T145,T152,T65	Yes	T145,T152,T65	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	INPUT
tl_uart3_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T1,T344,T294	Yes	T1,T344,T294	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	INPUT
tl_uart3_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T1,*T344,*T294	Yes	T1,T344,T294	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T1,T152,T344	Yes	T1,T152,T344	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T206,T269,T343	Yes	T206,T269,T343	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T206,T269,T343	Yes	T206,T269,T343	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	INPUT
tl_i2c0_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T343,T38,T350	Yes	T343,T38,T350	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T206,T269	Yes	T152,T206,T65	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T152,T206,T269	Yes	T152,T206,T65	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T86	Yes	T57,T85,T86	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T206,*T269,*T343	Yes	T206,T269,T343	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T206,T212,T269	Yes	T206,T212,T269	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T206,T212,T269	Yes	T206,T212,T269	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	INPUT
tl_i2c1_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T212,T360,T361	Yes	T212,T360,T361	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T206,T212	Yes	T152,T206,T65	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T152,T206,T212	Yes	T152,T206,T65	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T86	Yes	T57,T85,T86	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T206,*T212,*T269	Yes	T206,T212,T269	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T206,T356,T269	Yes	T206,T356,T269	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T206,T356,T269	Yes	T206,T356,T269	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	INPUT
tl_i2c2_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T356,T343,T38	Yes	T356,T343,T38	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T206,T356	Yes	T152,T206,T65	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T152,T206,T356	Yes	T152,T206,T65	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T206,*T356,*T269	Yes	T206,T356,T269	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T152,T206,T65	Yes	T152,T206,T65	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T211,T153,T213	Yes	T211,T153,T213	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T211,T153,T213	Yes	T211,T153,T213	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T211,T65,T153	Yes	T211,T65,T153	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T211,T65,T153	Yes	T211,T65,T153	INPUT
tl_pattgen_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T87,T124	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T211,T153,T213	Yes	T211,T153,T213	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T211,T153,T213	Yes	T211,T65,T153	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T211,T153,T213	Yes	T211,T65,T153	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T86,T87	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T86,T87	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T211,*T153,*T213	Yes	T211,T153,T213	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T211,T65,T153	Yes	T211,T65,T153	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T214,T249,T755	Yes	T214,T249,T755	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T214,T249,T755	Yes	T214,T249,T755	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T65,T214,T249	Yes	T65,T214,T249	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T65,T214,T249	Yes	T65,T214,T249	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T214,T249,T755	Yes	T214,T249,T755	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T214,T249,T755	Yes	T65,T214,T249	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T214,T249,T755	Yes	T65,T214,T249	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T214,*T249,*T755	Yes	T214,T249,T755	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T65,T214,T249	Yes	T65,T214,T249	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T13,T22,T23	Yes	T13,T22,T23	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T22,T23	Yes	T2,T13,T65	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T13,T22,T23	Yes	T2,T13,T65	INPUT
tl_gpio_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T57,*T85,*T87	Yes	T57,T85,T87	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T5,T206,T10	Yes	T5,T206,T10	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T5,T206,T10	Yes	T5,T206,T10	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T5,T206,T65	Yes	T5,T206,T65	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T5,T206,T65	Yes	T5,T206,T65	INPUT
tl_spi_device_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T5,T206,T10	Yes	T5,T206,T10	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T206,T10	Yes	T5,T206,T10	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T5,T206,T65	Yes	T5,T206,T10	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T86,T87	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T5,*T206,*T65	Yes	T5,T206,T10	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T5,T206,T65	Yes	T5,T206,T65	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T193,T253,T153	Yes	T193,T253,T153	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T193,T253,T153	Yes	T193,T253,T153	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T193,T65,T253	Yes	T193,T65,T253	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T193,T65,T253	Yes	T193,T65,T253	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T193,T253,T153	Yes	T193,T253,T153	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T193,T253,T153	Yes	T193,T65,T253	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T193,T253,T249	Yes	T193,T65,T253	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T193,*T253,*T153	Yes	T193,T253,T153	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T193,T65,T253	Yes	T193,T65,T253	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T28,*T42	Yes	T2,T28,T42	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T2,T28,T42	Yes	T2,T28,T42	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T47,T145	Yes	T1,T47,T145	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T47,T145	Yes	T1,T47,T145	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T47,T145	Yes	T1,T47,T145	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T86,T87	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T149,T151,T760	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T47,*T145	Yes	T1,T47,T145	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T51,*T52,*T57	Yes	T51,T52,T57	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T149,*T150,*T151	Yes	T149,T150,T151	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T96,*T123,*T152	Yes	T96,T123,T152	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T3,T4,T28	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T42,T96,T71	Yes	T42,T96,T71	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T42,T96,T71	Yes	T42,T96,T71	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T42,T96,T71	Yes	T42,T96,T71	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T42,T96,T71	Yes	T42,T96,T71	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T42,T5,T43	Yes	T42,T71,T5	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T44,T45	Yes	T69,T65,T44	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T42,T96,T5	Yes	T42,T96,T71	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T324,*T325,*T326	Yes	T324,T325,T326	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T96,*T5,*T6	Yes	T42,T96,T71	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T42,T96,T71	Yes	T42,T96,T71	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T86,T87	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T40,T126	Yes	T6,T40,T126	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T40,T126	Yes	T6,T65,T40	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T85,T87,T124	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T28	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T4,T42,T70	Yes	T4,T42,T70	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T4,T42,T70	Yes	T4,T42,T70	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T4,T42,T70	Yes	T4,T42,T70	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T4,T42,T70	Yes	T4,T42,T70	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T86,T87	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T4,T42,T70	Yes	T4,T42,T70	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T70,T71	Yes	T4,T70,T71	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T4,T42,T70	Yes	T4,T42,T70	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T86,T87	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T4,*T70,*T71	Yes	T4,T42,T70	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T4,T42,T70	Yes	T4,T42,T70	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T28,T42,T43	Yes	T28,T42,T43	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T28,T42,T43	Yes	T28,T42,T43	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T28,T42,T43	Yes	T28,T42,T43	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T28,T42,T43	Yes	T28,T42,T43	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T28,T116,T173	Yes	T28,T116,T173	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T28,T6,T40	Yes	T28,T42,T43	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T28,T6,T40	Yes	T28,T42,T43	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T28,*T116,*T173	Yes	T28,T116,T173	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T28,T42,T43	Yes	T28,T42,T43	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T28	Yes	T3,T4,T28	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T28	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T28	Yes	T3,T4,T28	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T4,T28,T42	Yes	T4,T28,T42	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T86,T87	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T75,*T88,*T255	Yes	T75,T88,T255	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T28,T42	Yes	T4,T28,T42	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T4,T28,T42	Yes	T4,T28,T42	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T4,T28,T42	Yes	T4,T28,T42	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T4,T28,T42	Yes	T4,T28,T42	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T28,T70	Yes	T4,T28,T70	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T28,T42	Yes	T4,T28,T42	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T28,T42	Yes	T4,T28,T42	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T87	Yes	T76,T77,T255	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T28,*T42	Yes	T4,T28,T42	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T4,T28,T42	Yes	T4,T28,T42	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T18,T16,T201	Yes	T18,T16,T201	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T18,T16,T201	Yes	T18,T16,T201	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T65,T18,T16	Yes	T65,T18,T16	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T65,T18,T16	Yes	T65,T18,T16	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T16,T201	Yes	T18,T16,T201	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T16,T201	Yes	T65,T18,T16	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T18,T201,T469	Yes	T65,T18,T16	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T18,*T16,*T201	Yes	T18,T16,T201	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T65,T18,T16	Yes	T65,T18,T16	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T16,T110,T49	Yes	T16,T110,T49	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T16,T110,T49	Yes	T16,T110,T49	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T65,T16,T110	Yes	T65,T16,T110	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T65,T16,T110	Yes	T65,T16,T110	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T85,T86,T87	Yes	T85,T87,T124	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T16,T110,T49	Yes	T16,T110,T49	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T110,T49	Yes	T65,T16,T110	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T16,T110,T49	Yes	T65,T16,T110	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T86,T87	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T16,*T110,*T49	Yes	T16,T110,T49	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T65,T16,T110	Yes	T65,T16,T110	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T75,T88,T51	Yes	T75,T88,T51	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T85,T87,T124	Yes	T85,T86,T87	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T3,T4,T28	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T87,T124	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T85,T87,T124	Yes	T85,T87,T124	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T85,*T87,*T124	Yes	T85,T86,T87	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range