Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T51,T52,T177
0	1	Covered	T177,T178,T306
1	0	Covered	T51

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T51,T177,T178
1	Covered	T51,T52,T177

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T51,T177,T178
1	Covered	T51,T52,T177

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T178,T306
1	1	Covered	T51,T177,T178

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T177
1	0	Covered	T51,T177,T178
1	1	Covered	T177,T178,T306

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T51,T177,T178

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T51,T52,T177
0	Covered	T51,T177,T178

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T51,T52,T177
0	Covered	T51,T177,T178

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1088413684	1070491622	0	0
CheckNGreaterZero_A	2042	2042	0	0
GntImpliesReady_A	1088413684	8391	0	0
GntImpliesValid_A	1088413684	8391	0	0
GrantKnown_A	1088413684	1070491622	0	0
IdxKnown_A	1088413684	1070491622	0	0
IndexIsCorrect_A	1088413684	8391	0	0
NoReadyValidNoGrant_A	1088413684	0	0	0
Priority_A	1088413684	8391	0	0
ReadyAndValidImplyGrant_A	1088413684	8391	0	0
ReqAndReadyImplyGrant_A	1088413684	8391	0	0
ReqImpliesValid_A	1088413684	8391	0	0
ValidKnown_A	1088413684	1070491622	0	0
gen_data_port_assertion.DataFlow_A	1088413684	8391	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	1070491622	0	0
T1	444902	444786	0	0
T2	249846	249744	0	0
T3	343166	342804	0	0
T4	579964	579752	0	0
T28	504546	504220	0	0
T42	1883966	1883842	0	0
T70	441126	440900	0	0
T94	387548	387438	0	0
T95	166796	166680	0	0
T96	942116	941788	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T28	2	2	0	0
T42	2	2	0	0
T70	2	2	0	0
T94	2	2	0	0
T95	2	2	0	0
T96	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	8391	0	0
T30	207720	0	0	0
T58	198776	0	0	0
T157	249442	0	0	0
T177	163744	2798	0	0
T178	0	2798	0	0
T278	494226	0	0	0
T306	0	2795	0	0
T420	206502	0	0	0
T421	130520	0	0	0
T422	483588	0	0	0
T423	579344	0	0	0
T424	423380	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	8391	0	0
T30	207720	0	0	0
T58	198776	0	0	0
T157	249442	0	0	0
T177	163744	2798	0	0
T178	0	2798	0	0
T278	494226	0	0	0
T306	0	2795	0	0
T420	206502	0	0	0
T421	130520	0	0	0
T422	483588	0	0	0
T423	579344	0	0	0
T424	423380	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	1070491622	0	0
T1	444902	444786	0	0
T2	249846	249744	0	0
T3	343166	342804	0	0
T4	579964	579752	0	0
T28	504546	504220	0	0
T42	1883966	1883842	0	0
T70	441126	440900	0	0
T94	387548	387438	0	0
T95	166796	166680	0	0
T96	942116	941788	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	1070491622	0	0
T1	444902	444786	0	0
T2	249846	249744	0	0
T3	343166	342804	0	0
T4	579964	579752	0	0
T28	504546	504220	0	0
T42	1883966	1883842	0	0
T70	441126	440900	0	0
T94	387548	387438	0	0
T95	166796	166680	0	0
T96	942116	941788	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	8391	0	0
T30	207720	0	0	0
T58	198776	0	0	0
T157	249442	0	0	0
T177	163744	2798	0	0
T178	0	2798	0	0
T278	494226	0	0	0
T306	0	2795	0	0
T420	206502	0	0	0
T421	130520	0	0	0
T422	483588	0	0	0
T423	579344	0	0	0
T424	423380	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	8391	0	0
T30	207720	0	0	0
T58	198776	0	0	0
T157	249442	0	0	0
T177	163744	2798	0	0
T178	0	2798	0	0
T278	494226	0	0	0
T306	0	2795	0	0
T420	206502	0	0	0
T421	130520	0	0	0
T422	483588	0	0	0
T423	579344	0	0	0
T424	423380	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	8391	0	0
T30	207720	0	0	0
T58	198776	0	0	0
T157	249442	0	0	0
T177	163744	2798	0	0
T178	0	2798	0	0
T278	494226	0	0	0
T306	0	2795	0	0
T420	206502	0	0	0
T421	130520	0	0	0
T422	483588	0	0	0
T423	579344	0	0	0
T424	423380	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	8391	0	0
T30	207720	0	0	0
T58	198776	0	0	0
T157	249442	0	0	0
T177	163744	2798	0	0
T178	0	2798	0	0
T278	494226	0	0	0
T306	0	2795	0	0
T420	206502	0	0	0
T421	130520	0	0	0
T422	483588	0	0	0
T423	579344	0	0	0
T424	423380	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	8391	0	0
T30	207720	0	0	0
T58	198776	0	0	0
T157	249442	0	0	0
T177	163744	2798	0	0
T178	0	2798	0	0
T278	494226	0	0	0
T306	0	2795	0	0
T420	206502	0	0	0
T421	130520	0	0	0
T422	483588	0	0	0
T423	579344	0	0	0
T424	423380	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	1070491622	0	0
T1	444902	444786	0	0
T2	249846	249744	0	0
T3	343166	342804	0	0
T4	579964	579752	0	0
T28	504546	504220	0	0
T42	1883966	1883842	0	0
T70	441126	440900	0	0
T94	387548	387438	0	0
T95	166796	166680	0	0
T96	942116	941788	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088413684	8391	0	0
T30	207720	0	0	0
T58	198776	0	0	0
T157	249442	0	0	0
T177	163744	2798	0	0
T178	0	2798	0	0
T278	494226	0	0	0
T306	0	2795	0	0
T420	206502	0	0	0
T421	130520	0	0	0
T422	483588	0	0	0
T423	579344	0	0	0
T424	423380	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T51,T52,T177
0	1	Covered	T177,T178,T306
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T177,T178,T306
1	Covered	T51,T52,T177

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T177,T178,T306
1	Covered	T51,T52,T177

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T178,T306
1	1	Covered	T177,T178,T306

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T177
1	0	Covered	T177,T178,T306
1	1	Covered	T177,T178,T306

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T177,T178,T306

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T51,T52,T177
0	Covered	T177,T178,T306

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T51,T52,T177
0	Covered	T177,T178,T306

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	544206842	535245811	0	0
CheckNGreaterZero_A	1021	1021	0	0
GntImpliesReady_A	544206842	5200	0	0
GntImpliesValid_A	544206842	5200	0	0
GrantKnown_A	544206842	535245811	0	0
IdxKnown_A	544206842	535245811	0	0
IndexIsCorrect_A	544206842	5200	0	0
NoReadyValidNoGrant_A	544206842	0	0	0
Priority_A	544206842	5200	0	0
ReadyAndValidImplyGrant_A	544206842	5200	0	0
ReqAndReadyImplyGrant_A	544206842	5200	0	0
ReqImpliesValid_A	544206842	5200	0	0
ValidKnown_A	544206842	535245811	0	0
gen_data_port_assertion.DataFlow_A	544206842	5200	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	535245811	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	5200	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1734	0	0
T178	0	1734	0	0
T278	247113	0	0	0
T306	0	1732	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	5200	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1734	0	0
T178	0	1734	0	0
T278	247113	0	0	0
T306	0	1732	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	535245811	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	535245811	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	5200	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1734	0	0
T178	0	1734	0	0
T278	247113	0	0	0
T306	0	1732	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	5200	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1734	0	0
T178	0	1734	0	0
T278	247113	0	0	0
T306	0	1732	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	5200	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1734	0	0
T178	0	1734	0	0
T278	247113	0	0	0
T306	0	1732	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	5200	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1734	0	0
T178	0	1734	0	0
T278	247113	0	0	0
T306	0	1732	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	5200	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1734	0	0
T178	0	1734	0	0
T278	247113	0	0	0
T306	0	1732	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	535245811	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	5200	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1734	0	0
T178	0	1734	0	0
T278	247113	0	0	0
T306	0	1732	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T51,T52,T177
0	1	Covered	T177,T178,T306
1	0	Covered	T51

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T51,T177,T178
1	Covered	T51,T52,T177

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T51,T177,T178
1	Covered	T51,T52,T177

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T178,T306
1	1	Covered	T51,T177,T178

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T177
1	0	Covered	T51,T177,T178
1	1	Covered	T177,T178,T306

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T51,T177,T178

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T51,T52,T177
0	Covered	T51,T177,T178

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T51,T52,T177
0	Covered	T51,T177,T178

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	544206842	535245811	0	0
CheckNGreaterZero_A	1021	1021	0	0
GntImpliesReady_A	544206842	3191	0	0
GntImpliesValid_A	544206842	3191	0	0
GrantKnown_A	544206842	535245811	0	0
IdxKnown_A	544206842	535245811	0	0
IndexIsCorrect_A	544206842	3191	0	0
NoReadyValidNoGrant_A	544206842	0	0	0
Priority_A	544206842	3191	0	0
ReadyAndValidImplyGrant_A	544206842	3191	0	0
ReqAndReadyImplyGrant_A	544206842	3191	0	0
ReqImpliesValid_A	544206842	3191	0	0
ValidKnown_A	544206842	535245811	0	0
gen_data_port_assertion.DataFlow_A	544206842	3191	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	535245811	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	3191	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1064	0	0
T178	0	1064	0	0
T278	247113	0	0	0
T306	0	1063	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	3191	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1064	0	0
T178	0	1064	0	0
T278	247113	0	0	0
T306	0	1063	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	535245811	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	535245811	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	3191	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1064	0	0
T178	0	1064	0	0
T278	247113	0	0	0
T306	0	1063	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	3191	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1064	0	0
T178	0	1064	0	0
T278	247113	0	0	0
T306	0	1063	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	3191	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1064	0	0
T178	0	1064	0	0
T278	247113	0	0	0
T306	0	1063	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	3191	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1064	0	0
T178	0	1064	0	0
T278	247113	0	0	0
T306	0	1063	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	3191	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1064	0	0
T178	0	1064	0	0
T278	247113	0	0	0
T306	0	1063	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	535245811	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	3191	0	0
T30	103860	0	0	0
T58	99388	0	0	0
T157	124721	0	0	0
T177	81872	1064	0	0
T178	0	1064	0	0
T278	247113	0	0	0
T306	0	1063	0	0
T420	103251	0	0	0
T421	65260	0	0	0
T422	241794	0	0	0
T423	289672	0	0	0
T424	211690	0	0	0