Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3524194	1			T71	397		T72	54		T73	16
values[2]	713620	1			T71	87		T72	15		T73	15
values[3]	101927	1			T72	19		T73	15		T77	8
values[4]	54281	1			T73	15		T464	119		T545	660
values[5]	36642	1			T73	15		T464	84		T545	342
values[6]	27066	1			T73	15		T464	104		T545	256
values[7]	21213	1			T73	15		T464	89		T545	189
values[8]	18508	1			T73	15		T464	75		T545	156
values[9]	16231	1			T73	15		T464	99		T545	94
values[10]	15070	1			T73	15		T464	84		T545	84
values[11]	14005	1			T73	15		T464	102		T545	68
values[12]	13192	1			T73	15		T464	81		T545	50
values[13]	12593	1			T73	15		T464	100		T545	38
values[14]	12015	1			T73	15		T464	108		T545	25
values[15]	11259	1			T73	15		T464	91		T545	16
values[16]	10781	1			T73	15		T464	87		T545	22
values[17]	10553	1			T73	15		T464	67		T545	27
values[18]	10086	1			T73	15		T464	52		T545	33
values[19]	9738	1			T73	15		T464	59		T545	34
values[20]	9436	1			T73	15		T464	82		T545	34
values[21]	9414	1			T73	15		T464	93		T545	37
values[22]	9223	1			T73	15		T464	100		T545	22
values[23]	9101	1			T73	15		T464	60		T545	22
values[24]	8683	1			T73	16		T464	66		T545	17
values[25]	8240	1			T73	15		T464	47		T545	13
values[26]	8098	1			T73	15		T464	42		T545	18
values[27]	7822	1			T73	15		T464	44		T545	28
values[28]	7403	1			T73	16		T464	35		T545	19
values[29]	6910	1			T73	15		T464	47		T545	28
values[30]	6426	1			T73	15		T464	32		T545	34
values[31]	5895	1			T73	15		T464	37		T545	26
values[32]	5367	1			T73	15		T464	19		T545	23
values[33]	5013	1			T73	15		T464	14		T545	17
values[34]	4718	1			T73	15		T464	20		T545	18
values[35]	4402	1			T73	15		T464	22		T545	18
values[36]	4252	1			T73	15		T464	19		T545	15
values[37]	4100	1			T73	15		T464	16		T545	21
values[38]	3882	1			T73	16		T464	19		T545	19
values[39]	3688	1			T73	16		T464	16		T545	14
values[40]	3535	1			T73	16		T464	17		T545	19
values[41]	3440	1			T73	15		T464	19		T545	19
values[42]	3315	1			T73	15		T464	18		T545	14
values[43]	3405	1			T73	16		T464	10		T545	15
values[44]	3284	1			T73	15		T464	21		T545	13
values[45]	3301	1			T73	15		T464	19		T545	10
values[46]	3219	1			T73	15		T464	8		T545	12
values[47]	3052	1			T73	15		T464	7		T545	10
values[48]	3059	1			T73	15		T464	9		T545	11
values[49]	2916	1			T73	15		T464	2		T545	15
values[50]	2886	1			T73	15		T545	14		T546	6
values[51]	2815	1			T73	15		T545	11		T546	4
values[52]	2765	1			T73	15		T545	10		T546	2
values[53]	2669	1			T73	15		T545	14		T546	4
values[54]	2618	1			T73	15		T545	15		T546	3
values[55]	2599	1			T73	15		T545	8		T546	3
values[56]	2597	1			T73	15		T545	10		T546	7
values[57]	2527	1			T73	15		T545	17		T546	2
values[58]	2538	1			T73	16		T545	11		T546	2
values[59]	2462	1			T73	16		T545	11		T546	6
values[60]	2468	1			T73	16		T545	15		T546	9
values[61]	2706	1			T73	15		T545	19		T546	5
values[62]	4080	1			T73	15		T545	37		T546	15
values[63]	10632	1			T73	17		T545	143		T546	59
values[64]	253029	1			T73	2998		T545	601		T546	97

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4557544	1			T71	313		T72	67		T73	2055
values[2]	779780	1			T71	82		T72	25		T73	649
values[3]	84791	1			T71	3		T72	8		T73	214
values[4]	14774	1			T72	1		T73	84		T77	7
values[5]	5510	1			T73	30		T77	1		T464	4
values[6]	3343	1			T73	12		T464	2		T545	49
values[7]	2648	1			T73	3		T464	2		T545	59
values[8]	2224	1			T73	2		T464	2		T545	60
values[9]	1828	1			T73	2		T464	2		T545	52
values[10]	1554	1			T73	2		T464	2		T545	53
values[11]	1435	1			T73	2		T464	1		T545	45
values[12]	1197	1			T73	2		T464	2		T545	30
values[13]	1154	1			T73	2		T464	3		T545	30
values[14]	1028	1			T73	2		T464	2		T545	13
values[15]	1004	1			T73	2		T464	2		T545	11
values[16]	956	1			T73	2		T464	2		T545	21
values[17]	850	1			T73	2		T464	2		T545	16
values[18]	778	1			T73	2		T464	2		T545	10
values[19]	804	1			T73	2		T464	2		T545	14
values[20]	776	1			T73	2		T464	2		T545	17
values[21]	705	1			T73	2		T464	2		T545	17
values[22]	714	1			T73	2		T464	2		T545	26
values[23]	690	1			T73	2		T464	2		T545	12
values[24]	617	1			T73	2		T464	2		T545	14
values[25]	645	1			T73	2		T464	2		T545	20
values[26]	575	1			T73	2		T464	2		T545	11
values[27]	599	1			T73	2		T464	2		T545	8
values[28]	559	1			T73	2		T464	2		T545	12
values[29]	538	1			T73	2		T464	2		T545	7
values[30]	551	1			T73	2		T464	2		T545	13
values[31]	549	1			T73	2		T464	2		T545	17
values[32]	504	1			T73	2		T464	1		T545	16
values[33]	496	1			T73	2		T464	1		T545	12
values[34]	511	1			T73	2		T464	2		T545	15
values[35]	532	1			T73	2		T464	3		T545	13
values[36]	440	1			T73	2		T464	2		T545	17
values[37]	436	1			T73	2		T464	2		T545	14
values[38]	441	1			T73	2		T464	2		T545	15
values[39]	465	1			T73	2		T464	2		T545	16
values[40]	468	1			T73	2		T464	2		T545	12
values[41]	469	1			T73	2		T464	2		T545	13
values[42]	416	1			T73	2		T464	2		T545	8
values[43]	420	1			T73	2		T464	2		T545	8
values[44]	392	1			T73	2		T464	2		T545	4
values[45]	367	1			T73	2		T464	2		T545	6
values[46]	390	1			T73	2		T464	2		T545	6
values[47]	413	1			T73	2		T464	2		T545	12
values[48]	385	1			T73	2		T464	2		T545	10
values[49]	383	1			T73	2		T464	2		T545	7
values[50]	352	1			T73	2		T464	2		T545	6
values[51]	364	1			T73	2		T464	2		T545	8
values[52]	365	1			T73	2		T464	2		T545	7
values[53]	350	1			T73	2		T464	2		T545	7
values[54]	366	1			T73	2		T464	2		T545	8
values[55]	360	1			T73	2		T464	2		T545	9
values[56]	352	1			T73	2		T464	2		T545	16
values[57]	337	1			T73	2		T464	2		T545	11
values[58]	350	1			T73	2		T464	2		T545	7
values[59]	335	1			T73	2		T464	2		T545	7
values[60]	347	1			T73	2		T464	2		T545	7
values[61]	396	1			T73	2		T464	2		T545	18
values[62]	614	1			T73	2		T464	2		T545	22
values[63]	2521	1			T73	2		T464	4		T545	110
values[64]	25930	1			T73	443		T464	161		T545	287

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	522969	1			T71	3		T72	1		T73	15
values[2]	2472620	1			T71	359		T72	1		T73	15
values[3]	1173791	1			T71	93		T72	65		T73	15
values[4]	146910	1			T71	1		T72	23		T73	17
values[5]	75585	1			T72	1		T73	15		T464	158
values[6]	48846	1			T73	15		T464	136		T545	632
values[7]	35264	1			T73	15		T464	109		T545	397
values[8]	27456	1			T73	15		T464	116		T545	335
values[9]	23246	1			T73	15		T464	116		T545	291
values[10]	20513	1			T73	15		T464	124		T545	228
values[11]	18082	1			T73	15		T464	92		T545	213
values[12]	16361	1			T73	15		T464	91		T545	215
values[13]	15465	1			T73	15		T464	103		T545	180
values[14]	14587	1			T73	15		T464	96		T545	164
values[15]	14078	1			T73	15		T464	107		T545	125
values[16]	13501	1			T73	15		T464	96		T545	78
values[17]	12890	1			T73	15		T464	71		T545	75
values[18]	12413	1			T73	16		T464	67		T545	51
values[19]	11899	1			T73	15		T464	87		T545	57
values[20]	11475	1			T73	15		T464	54		T545	71
values[21]	11080	1			T73	16		T464	37		T545	69
values[22]	10352	1			T73	15		T464	53		T545	45
values[23]	9987	1			T73	15		T464	65		T545	55
values[24]	9774	1			T73	15		T464	83		T545	45
values[25]	9124	1			T73	15		T464	73		T545	59
values[26]	8795	1			T73	16		T464	73		T545	73
values[27]	8394	1			T73	15		T464	63		T545	60
values[28]	8094	1			T73	15		T464	52		T545	53
values[29]	7753	1			T73	15		T464	62		T545	47
values[30]	7246	1			T73	15		T464	64		T545	55
values[31]	6610	1			T73	15		T464	54		T545	51
values[32]	6433	1			T73	16		T464	32		T545	44
values[33]	6137	1			T73	15		T464	29		T545	49
values[34]	5448	1			T73	15		T464	18		T545	36
values[35]	4908	1			T73	15		T464	27		T545	43
values[36]	4602	1			T73	16		T464	19		T545	37
values[37]	4504	1			T73	16		T464	11		T545	42
values[38]	4273	1			T73	15		T464	12		T545	41
values[39]	4086	1			T73	15		T464	8		T545	40
values[40]	3994	1			T73	15		T464	8		T545	32
values[41]	3879	1			T73	15		T464	12		T545	44
values[42]	3714	1			T73	15		T464	9		T545	36
values[43]	3650	1			T73	15		T464	11		T545	42
values[44]	3548	1			T73	15		T464	11		T545	43
values[45]	3505	1			T73	15		T464	6		T545	41
values[46]	3370	1			T73	15		T464	22		T545	51
values[47]	3389	1			T73	15		T464	13		T545	46
values[48]	3379	1			T73	15		T464	9		T545	59
values[49]	3273	1			T73	15		T464	12		T545	55
values[50]	3151	1			T73	15		T464	11		T545	42
values[51]	3179	1			T73	15		T464	9		T545	38
values[52]	3013	1			T73	15		T464	10		T545	29
values[53]	2941	1			T73	15		T464	4		T545	26
values[54]	2939	1			T73	15		T464	19		T545	14
values[55]	2901	1			T73	15		T464	18		T545	15
values[56]	2880	1			T73	15		T464	1		T545	20
values[57]	2731	1			T73	15		T464	6		T545	24
values[58]	2734	1			T73	15		T464	1		T545	19
values[59]	2768	1			T73	15		T464	1		T545	16
values[60]	2724	1			T73	15		T545	25		T546	9
values[61]	2906	1			T73	15		T545	39		T546	8
values[62]	3600	1			T73	15		T545	43		T546	25
values[63]	8576	1			T73	17		T545	140		T546	74
values[64]	241461	1			T73	3046		T545	465		T546	205