Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2048961	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

39630751

1

T1

7327

T2

13453

T3

7047

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29030091	1			T1	3280		T2	5553		T3	3201
values[0x0]	11110837	1			T1	4047		T2	7900		T3	3846
values[0x1]	1538784	1			T1	342		T2	942		T3	450

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	643185	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41036527

1

T1

7669

T2

14395

T3

7497

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19691392	1			T1	3835		T2	7198		T3	3749
valid_sources[0x01]	19691231	1			T1	3834		T2	7197		T3	3748
valid_sources[0x02]	36694	1			T134	911		T393	78		T390	110
valid_sources[0x03]	36942	1			T134	823		T393	95		T390	129
valid_sources[0x04]	37201	1			T134	733		T393	95		T390	121
valid_sources[0x05]	36902	1			T134	815		T393	95		T390	106
valid_sources[0x06]	37151	1			T134	792		T393	60		T390	139
valid_sources[0x07]	37266	1			T134	905		T393	78		T390	128
valid_sources[0x08]	37075	1			T134	738		T393	84		T390	133
valid_sources[0x09]	36770	1			T134	788		T393	91		T390	123
valid_sources[0x0a]	37928	1			T134	805		T393	82		T390	137
valid_sources[0x0b]	36620	1			T134	850		T393	73		T390	113
valid_sources[0x0c]	36153	1			T134	751		T393	96		T390	132
valid_sources[0x0d]	36869	1			T134	800		T393	98		T390	116
valid_sources[0x0e]	37388	1			T134	811		T393	95		T390	135
valid_sources[0x0f]	36905	1			T134	747		T393	68		T390	126
valid_sources[0x10]	37066	1			T134	727		T393	114		T390	116
valid_sources[0x11]	37056	1			T134	750		T393	90		T390	93
valid_sources[0x12]	37548	1			T134	755		T393	91		T390	118
valid_sources[0x13]	37435	1			T134	814		T393	93		T390	135
valid_sources[0x14]	37027	1			T134	789		T393	69		T390	121
valid_sources[0x15]	36804	1			T46	5		T134	775		T393	77
valid_sources[0x16]	37680	1			T46	2		T134	780		T393	74
valid_sources[0x17]	37273	1			T134	781		T393	85		T390	114
valid_sources[0x18]	35909	1			T134	723		T393	78		T390	148
valid_sources[0x19]	36872	1			T46	2		T134	747		T393	73
valid_sources[0x1a]	37217	1			T134	752		T393	93		T390	148
valid_sources[0x1b]	37029	1			T134	787		T393	72		T390	87
valid_sources[0x1c]	38211	1			T134	782		T393	82		T390	139
valid_sources[0x1d]	36817	1			T134	835		T393	106		T390	126
valid_sources[0x1e]	36024	1			T134	764		T393	87		T390	110
valid_sources[0x1f]	36486	1			T46	7		T134	756		T393	89
valid_sources[0x20]	39960	1			T134	767		T393	84		T390	106

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28320348

1

T1

3280

T2

5553

T3

3201

values[0x0]

all_enables

biggest_size

11058766

1

T1

4047

T2

7900

T3

3846

values[0x1]

all_enables

biggest_size

251637

1

T75

26

T76

18

T46

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2737026	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

432387

1

T71

80

T72

6

T73

562

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1073905	1			T71	154		T72	33		T73	1330
values[0x0]	1022966	1			T71	179		T72	29		T73	1315
values[0x1]	1072542	1			T71	151		T72	26		T73	1310

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2119091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1050322

1

T71

171

T72

21

T73

1314

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48295	1			T71	7		T72	1		T73	66
valid_sources[0x01]	49390	1			T71	9		T72	2		T73	69
valid_sources[0x02]	48855	1			T71	6		T73	60		T77	21
valid_sources[0x03]	49011	1			T71	6		T72	3		T73	51
valid_sources[0x04]	49254	1			T71	10		T73	62		T77	15
valid_sources[0x05]	50863	1			T71	5		T72	2		T73	61
valid_sources[0x06]	48680	1			T71	7		T72	2		T73	64
valid_sources[0x07]	49128	1			T71	10		T72	3		T73	56
valid_sources[0x08]	49825	1			T71	3		T72	1		T73	63
valid_sources[0x09]	50088	1			T71	13		T72	1		T73	54
valid_sources[0x0a]	49732	1			T71	2		T72	2		T73	65
valid_sources[0x0b]	49444	1			T71	6		T72	1		T73	57
valid_sources[0x0c]	49282	1			T71	7		T72	1		T73	65
valid_sources[0x0d]	50394	1			T71	5		T72	2		T73	63
valid_sources[0x0e]	49103	1			T71	15		T73	50		T77	12
valid_sources[0x0f]	49053	1			T71	9		T72	1		T73	70
valid_sources[0x10]	49179	1			T71	8		T72	1		T73	60
valid_sources[0x11]	50054	1			T71	4		T72	4		T73	59
valid_sources[0x12]	48812	1			T71	13		T72	1		T73	58
valid_sources[0x13]	49829	1			T71	6		T73	66		T77	24
valid_sources[0x14]	49444	1			T71	8		T73	57		T77	18
valid_sources[0x15]	49653	1			T71	7		T72	1		T73	58
valid_sources[0x16]	50238	1			T71	11		T72	2		T73	74
valid_sources[0x17]	50700	1			T71	7		T72	2		T73	59
valid_sources[0x18]	48911	1			T71	8		T72	1		T73	57
valid_sources[0x19]	48427	1			T71	15		T72	1		T73	54
valid_sources[0x1a]	49791	1			T71	4		T73	79		T77	22
valid_sources[0x1b]	49349	1			T71	3		T72	1		T73	66
valid_sources[0x1c]	49421	1			T71	7		T73	60		T77	25
valid_sources[0x1d]	49431	1			T71	10		T72	2		T73	52
valid_sources[0x1e]	50239	1			T71	1		T72	1		T73	66
valid_sources[0x1f]	50117	1			T71	7		T72	2		T73	56
valid_sources[0x20]	50074	1			T71	4		T72	2		T73	59

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45341

1

T71

7

T73

48

T77

27

values[0x0]

all_enables

biggest_size

341901

1

T71

64

T72

5

T73

456

values[0x1]

all_enables

biggest_size

45145

1

T71

9

T72

1

T73

58

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2922272	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

476559

1

T71

59

T72

8

T73

522

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1162899	1			T71	123		T72	41		T73	1223
values[0x0]	1071000	1			T71	128		T72	27		T73	1172
values[0x1]	1164932	1			T71	147		T72	33		T73	1207

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2243250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1155581

1

T71

136

T72

38

T73

1214

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52798	1			T71	10		T73	43		T77	15
valid_sources[0x01]	52380	1			T72	2		T73	72		T77	8
valid_sources[0x02]	52407	1			T71	2		T73	50		T77	18
valid_sources[0x03]	52436	1			T71	4		T72	3		T73	55
valid_sources[0x04]	52780	1			T71	3		T72	4		T73	63
valid_sources[0x05]	53538	1			T71	20		T72	1		T73	47
valid_sources[0x06]	53506	1			T71	5		T73	54		T77	19
valid_sources[0x07]	53044	1			T71	1		T72	6		T73	54
valid_sources[0x08]	52830	1			T71	5		T73	71		T77	21
valid_sources[0x09]	53724	1			T71	15		T72	2		T73	67
valid_sources[0x0a]	54166	1			T71	8		T73	62		T77	15
valid_sources[0x0b]	53617	1			T71	2		T72	1		T73	46
valid_sources[0x0c]	52899	1			T73	52		T77	32		T119	73
valid_sources[0x0d]	53198	1			T71	26		T72	1		T73	59
valid_sources[0x0e]	52337	1			T71	2		T73	51		T77	7
valid_sources[0x0f]	52522	1			T71	8		T72	1		T73	56
valid_sources[0x10]	53263	1			T71	6		T72	1		T73	55
valid_sources[0x11]	52736	1			T71	3		T73	70		T77	37
valid_sources[0x12]	53254	1			T71	19		T73	56		T77	12
valid_sources[0x13]	52149	1			T71	2		T73	51		T77	22
valid_sources[0x14]	52416	1			T71	20		T73	62		T77	44
valid_sources[0x15]	53421	1			T71	4		T72	5		T73	57
valid_sources[0x16]	52762	1			T72	1		T73	61		T77	28
valid_sources[0x17]	53131	1			T71	15		T73	58		T77	20
valid_sources[0x18]	52146	1			T71	8		T73	60		T77	20
valid_sources[0x19]	54110	1			T72	3		T73	46		T77	9
valid_sources[0x1a]	53224	1			T71	6		T72	1		T73	54
valid_sources[0x1b]	52260	1			T71	10		T73	64		T77	29
valid_sources[0x1c]	53051	1			T72	1		T73	65		T77	29
valid_sources[0x1d]	54166	1			T71	5		T73	64		T77	42
valid_sources[0x1e]	53347	1			T71	3		T73	57		T77	33
valid_sources[0x1f]	52297	1			T71	20		T72	1		T73	43
valid_sources[0x20]	52721	1			T72	4		T73	54		T77	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49998

1

T71

6

T72

1

T73

44

values[0x0]

all_enables

biggest_size

376210

1

T71

45

T72

7

T73

420

values[0x1]

all_enables

biggest_size

50351

1

T71

8

T73

58

T77

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2766061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

436156

1

T71

62

T72

13

T73

583

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1084357	1			T71	151		T72	38		T73	1344
values[0x0]	1033013	1			T71	155		T72	27		T73	1324
values[0x1]	1084847	1			T71	150		T72	26		T73	1333

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2142334	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1059883

1

T71

147

T72

35

T73

1358

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49983	1			T73	62		T77	19		T119	33
valid_sources[0x01]	50767	1			T71	28		T72	2		T73	64
valid_sources[0x02]	48647	1			T73	58		T77	17		T119	67
valid_sources[0x03]	49280	1			T71	9		T72	2		T73	65
valid_sources[0x04]	49841	1			T71	2		T72	1		T73	62
valid_sources[0x05]	49803	1			T71	13		T72	3		T73	55
valid_sources[0x06]	49901	1			T71	6		T72	6		T73	64
valid_sources[0x07]	49839	1			T72	1		T73	74		T77	21
valid_sources[0x08]	50209	1			T71	12		T72	5		T73	70
valid_sources[0x09]	51226	1			T71	3		T72	1		T73	70
valid_sources[0x0a]	50183	1			T71	25		T72	5		T73	57
valid_sources[0x0b]	49932	1			T71	4		T72	2		T73	53
valid_sources[0x0c]	49845	1			T71	6		T73	61		T77	23
valid_sources[0x0d]	49453	1			T72	1		T73	62		T77	18
valid_sources[0x0e]	49807	1			T71	9		T72	1		T73	64
valid_sources[0x0f]	49140	1			T71	2		T72	1		T73	72
valid_sources[0x10]	50305	1			T72	4		T73	52		T77	26
valid_sources[0x11]	50211	1			T71	1		T73	70		T77	21
valid_sources[0x12]	48956	1			T71	21		T72	2		T73	62
valid_sources[0x13]	49392	1			T71	16		T72	1		T73	53
valid_sources[0x14]	50187	1			T71	29		T73	66		T77	13
valid_sources[0x15]	49843	1			T71	14		T73	55		T77	26
valid_sources[0x16]	50064	1			T71	2		T73	64		T77	11
valid_sources[0x17]	50268	1			T71	13		T72	1		T73	73
valid_sources[0x18]	49689	1			T71	2		T73	59		T77	8
valid_sources[0x19]	49457	1			T71	3		T73	58		T77	23
valid_sources[0x1a]	50962	1			T71	5		T72	1		T73	63
valid_sources[0x1b]	49616	1			T71	18		T72	5		T73	71
valid_sources[0x1c]	49970	1			T71	1		T72	1		T73	73
valid_sources[0x1d]	49577	1			T71	25		T72	1		T73	54
valid_sources[0x1e]	50874	1			T71	1		T72	2		T73	66
valid_sources[0x1f]	49653	1			T71	5		T72	2		T73	55
valid_sources[0x20]	50232	1			T73	52		T77	27		T119	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45752

1

T71

4

T72

2

T73

61

values[0x0]

all_enables

biggest_size

344288

1

T71

51

T72

9

T73

455

values[0x1]

all_enables

biggest_size

46116

1

T71

7

T72

2

T73

67