Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525453196	59656867	0	0
DepthKnown_A	525453196	525345447	0	0
RvalidKnown_A	525453196	525345447	0	0
WreadyKnown_A	525453196	525345447	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	59656867	0	0
T1	140082	19393	0	0
T2	232106	30171	0	0
T3	102505	10816	0	0
T4	242546	31821	0	0
T5	106859	387795	0	0
T42	134765	147095	0	0
T60	221697	28935	0	0
T85	506673	47254	0	0
T86	100459	12299	0	0
T87	42206	3461	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525453196	46328528	0	0
DepthKnown_A	525453196	525345447	0	0
RvalidKnown_A	525453196	525345447	0	0
WreadyKnown_A	525453196	525345447	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	46328528	0	0
T1	140082	14094	0	0
T2	232106	20706	0	0
T3	102505	8914	0	0
T4	242546	22151	0	0
T5	106859	195144	0	0
T42	134765	128096	0	0
T60	221697	19409	0	0
T85	506673	41504	0	0
T86	100459	9562	0	0
T87	42206	1868	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525453196	46239771	0	0
DepthKnown_A	525453196	525345447	0	0
RvalidKnown_A	525453196	525345447	0	0
WreadyKnown_A	525453196	525345447	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	46239771	0	0
T1	140082	7953	0	0
T2	232106	14776	0	0
T3	102505	7619	0	0
T4	242546	15718	0	0
T5	106859	32337	0	0
T42	134765	187304	0	0
T60	221697	13810	0	0
T85	506673	53989	0	0
T86	100459	8660	0	0
T87	42206	459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525453196	39397246	0	0
DepthKnown_A	525453196	525345447	0	0
RvalidKnown_A	525453196	525345447	0	0
WreadyKnown_A	525453196	525345447	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	39397246	0	0
T1	140082	7669	0	0
T2	232106	14395	0	0
T3	102505	7497	0	0
T4	242546	15325	0	0
T5	106859	30645	0	0
T42	134765	119901	0	0
T60	221697	13430	0	0
T85	506673	53678	0	0
T86	100459	8075	0	0
T87	42206	351	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	525345447	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608666916	87886	0	0
DepthKnown_A	608666916	608543192	0	0
RvalidKnown_A	608666916	608543192	0	0
WreadyKnown_A	608666916	608543192	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	87886	0	0
T1	140082	26	0	0
T2	232106	151	0	0
T3	102505	13	0	0
T4	242546	153	0	0
T5	106859	152	0	0
T42	134765	34	0	0
T60	221697	151	0	0
T85	506673	237	0	0
T86	100459	34	0	0
T87	42206	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608666916	90617	0	0
DepthKnown_A	608666916	608543192	0	0
RvalidKnown_A	608666916	608543192	0	0
WreadyKnown_A	608666916	608543192	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	90617	0	0
T1	140082	26	0	0
T2	232106	151	0	0
T3	102505	13	0	0
T4	242546	153	0	0
T5	106859	152	0	0
T42	134765	34	0	0
T60	221697	151	0	0
T85	506673	237	0	0
T86	100459	34	0	0
T87	42206	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608666916	53387	0	0
DepthKnown_A	608666916	608543192	0	0
RvalidKnown_A	608666916	608543192	0	0
WreadyKnown_A	608666916	608543192	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	53387	0	0
T1	140082	23	0	0
T2	232106	95	0	0
T3	102505	12	0	0
T4	242546	97	0	0
T5	106859	143	0	0
T42	134765	5	0	0
T60	221697	95	0	0
T85	506673	234	0	0
T86	100459	33	0	0
T87	42206	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608666916	53387	0	0
DepthKnown_A	608666916	608543192	0	0
RvalidKnown_A	608666916	608543192	0	0
WreadyKnown_A	608666916	608543192	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	53387	0	0
T1	140082	23	0	0
T2	232106	95	0	0
T3	102505	12	0	0
T4	242546	97	0	0
T5	106859	143	0	0
T42	134765	5	0	0
T60	221697	95	0	0
T85	506673	234	0	0
T86	100459	33	0	0
T87	42206	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608666916	34499	0	0
DepthKnown_A	608666916	608543192	0	0
RvalidKnown_A	608666916	608543192	0	0
WreadyKnown_A	608666916	608543192	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	34499	0	0
T1	140082	3	0	0
T2	232106	56	0	0
T3	102505	1	0	0
T4	242546	56	0	0
T5	106859	9	0	0
T6	0	49	0	0
T42	134765	29	0	0
T60	221697	56	0	0
T85	506673	3	0	0
T86	100459	1	0	0
T87	42206	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608666916	37230	0	0
DepthKnown_A	608666916	608543192	0	0
RvalidKnown_A	608666916	608543192	0	0
WreadyKnown_A	608666916	608543192	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	37230	0	0
T1	140082	3	0	0
T2	232106	56	0	0
T3	102505	1	0	0
T4	242546	56	0	0
T5	106859	9	0	0
T6	0	49	0	0
T42	134765	29	0	0
T60	221697	56	0	0
T85	506673	3	0	0
T86	100459	1	0	0
T87	42206	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608666916	608543192	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0