Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
rst_shadowed_ni |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
clk_main_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_main_ni |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
clk_io_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_io_ni |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
clk_usb_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_usb_ni |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
clk_aon_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_aon_ni |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
rst_io_div2_ni |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
rst_io_div4_ni |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
rst_root_ni |
Yes |
Yes |
T5,T6,T7 |
Yes |
T1,T2,T3 |
INPUT |
rst_root_main_ni |
Yes |
Yes |
T5,T6,T7 |
Yes |
T1,T2,T3 |
INPUT |
rst_root_io_ni |
Yes |
Yes |
T5,T6,T7 |
Yes |
T1,T2,T3 |
INPUT |
rst_root_io_div2_ni |
Yes |
Yes |
T5,T6,T7 |
Yes |
T1,T2,T3 |
INPUT |
rst_root_io_div4_ni |
Yes |
Yes |
T5,T6,T7 |
Yes |
T1,T2,T3 |
INPUT |
rst_root_usb_ni |
Yes |
Yes |
T5,T6,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T169,T45,T102 |
Yes |
T169,T45,T102 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T169,T45,T102 |
Yes |
T169,T45,T102 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[6:0] |
Yes |
Yes |
*T71,*T72,*T73 |
Yes |
T71,T72,T73 |
INPUT |
tl_i.a_address[16:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[21:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[22] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[29:23] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T7,*T64,*T74 |
Yes |
T7,T64,T74 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T71,T72,T73 |
Yes |
T71,T72,T73 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T75,T76,T46 |
Yes |
T75,T76,T46 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T71,T72,T77 |
Yes |
T71,T72,T77 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T45,T102,T83 |
Yes |
T45,T102,T83 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T71,T77,T119 |
Yes |
T71,T72,T77 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T75,*T71,*T77 |
Yes |
T64,T139,T75 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T71,T72,T77 |
Yes |
T71,T77,T119 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T169,*T45,*T102 |
Yes |
T169,T45,T102 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T102,T78,T751 |
Yes |
T102,T78,T751 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T78,T81,T82 |
Yes |
T78,T81,T143 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T78,T81,T143 |
Yes |
T78,T81,T82 |
INPUT |
alert_rx_i[1].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[1].ack_p |
Yes |
Yes |
T78,T75,T752 |
Yes |
T78,T75,T752 |
INPUT |
alert_rx_i[1].ping_n |
Yes |
Yes |
T78,T81,T82 |
Yes |
T78,T81,T82 |
INPUT |
alert_rx_i[1].ping_p |
Yes |
Yes |
T78,T81,T82 |
Yes |
T78,T81,T82 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T102,T78,T751 |
Yes |
T102,T78,T751 |
OUTPUT |
alert_tx_o[1].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[1].alert_p |
Yes |
Yes |
T78,T75,T752 |
Yes |
T78,T75,T752 |
OUTPUT |
pwr_i.usb_ip_clk_en |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
INPUT |
pwr_i.io_ip_clk_en |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
INPUT |
pwr_i.main_ip_clk_en |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
INPUT |
pwr_o.usb_status |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
pwr_o.io_status |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
pwr_o.main_status |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
scanmode_i[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
lc_hw_debug_en_i[3:0] |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
INPUT |
lc_clk_byp_req_i[3:0] |
Yes |
Yes |
T5,T44,T64 |
Yes |
T5,T44,T64 |
INPUT |
lc_clk_byp_ack_o[3:0] |
Yes |
Yes |
T5,T44,T64 |
Yes |
T5,T44,T64 |
OUTPUT |
io_clk_byp_req_o[3:0] |
Yes |
Yes |
T5,T44,T64 |
Yes |
T5,T44,T64 |
OUTPUT |
io_clk_byp_ack_i[3:0] |
Yes |
Yes |
T5,T44,T64 |
Yes |
T5,T44,T64 |
INPUT |
all_clk_byp_req_o[3:0] |
Yes |
Yes |
T45,T64,T114 |
Yes |
T45,T114,T115 |
OUTPUT |
all_clk_byp_ack_i[3:0] |
Yes |
Yes |
T45,T64,T114 |
Yes |
T45,T114,T115 |
INPUT |
hi_speed_sel_o[3:0] |
Yes |
Yes |
T2,T5,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
calib_rdy_i[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T2,T5,T4 |
INPUT |
jitter_en_o[3:0] |
Yes |
Yes |
T104,T108,T113 |
Yes |
T104,T108,T112 |
OUTPUT |
div_step_down_req_i[3:0] |
Yes |
Yes |
T5,T44,T64 |
Yes |
T5,T44,T64 |
INPUT |
cg_en_o.usb_peri[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.io_peri[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.io_div2_peri[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.io_div4_peri[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.io_div4_timers[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.main_secure[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.io_div4_secure[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.io_div2_infra[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.io_infra[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.usb_infra[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.main_infra[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.io_div4_infra[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.main_otbn[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.main_kmac[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.main_hmac[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.main_aes[3:0] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
cg_en_o.aon_timers[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.aon_peri[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.aon_secure[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.io_div2_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.usb_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.io_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.main_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.aon_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.io_div4_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
clocks_o.clk_usb_peri |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_peri |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_div2_peri |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_div4_peri |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_div4_timers |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_main_secure |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_div4_secure |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_div2_infra |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_infra |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_usb_infra |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_main_infra |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_div4_infra |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_main_otbn |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_main_kmac |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_main_hmac |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_main_aes |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_aon_timers |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_aon_peri |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_aon_secure |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_div2_powerup |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_usb_powerup |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_powerup |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_main_powerup |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_aon_powerup |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
clocks_o.clk_io_div4_powerup |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |