Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T5,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T64,*T74	Yes	T7,T64,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T46	Yes	T75,T76,T46	INPUT
tl_i.a_valid	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	INPUT
tl_o.a_ready	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T253,*T46	Yes	T74,T253,T46	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T42,*T6,*T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T78,T145	Yes	T2,T78,T145	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T144,T81	Yes	T78,T144,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T144,T81	Yes	T78,T144,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T78,T145	Yes	T2,T78,T145	OUTPUT
cio_rx_i	Yes	Yes	T2,T5,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T42,T6,T83	Yes	T42,T6,T83	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T169,T103,T83	Yes	T169,T103,T83	OUTPUT
intr_tx_empty_o	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
intr_rx_watermark_o	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
intr_tx_done_o	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
intr_rx_overflow_o	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T5,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T64,*T74	Yes	T7,T64,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T46	Yes	T75,T76,T46	INPUT
tl_i.a_valid	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	INPUT
tl_o.a_ready	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_error	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T73,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T253,*T46	Yes	T74,T253,T46	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T73,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T42,*T6,*T169	Yes	T42,T6,T169	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T42,T6,T169	Yes	T42,T6,T169	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T145,T144	Yes	T78,T145,T144	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T144,T81	Yes	T78,T144,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T144,T81	Yes	T78,T144,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T145,T144	Yes	T78,T145,T144	OUTPUT
cio_rx_i	Yes	Yes	T2,T5,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T42,T6,T43	Yes	T42,T6,T43	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T169,T103,T210	Yes	T169,T103,T210	OUTPUT
intr_tx_empty_o	Yes	Yes	T103,T210,T211	Yes	T103,T210,T211	OUTPUT
intr_rx_watermark_o	Yes	Yes	T103,T210,T211	Yes	T103,T210,T211	OUTPUT
intr_tx_done_o	Yes	Yes	T103,T210,T340	Yes	T103,T210,T340	OUTPUT
intr_rx_overflow_o	Yes	Yes	T103,T210,T340	Yes	T103,T210,T340	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T5,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T103,T206,T207	Yes	T103,T206,T207	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T103,T206,T207	Yes	T103,T206,T207	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T64,*T74	Yes	T7,T64,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T46	Yes	T75,T76,T46	INPUT
tl_i.a_valid	Yes	Yes	T103,T145,T206	Yes	T103,T145,T206	INPUT
tl_o.a_ready	Yes	Yes	T103,T145,T206	Yes	T103,T145,T206	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T103,T206,T207	Yes	T103,T206,T207	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T103,T145,T206	Yes	T103,T145,T206	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T103,T145,T206	Yes	T103,T145,T206	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T46,*T47,*T71	Yes	T46,T47,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T103,*T206,*T207	Yes	T103,T206,T207	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T103,T145,T206	Yes	T103,T145,T206	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T145,T757	Yes	T78,T145,T757	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T81,T82	Yes	T78,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T81,T82	Yes	T78,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T145,T757	Yes	T78,T145,T757	OUTPUT
cio_rx_i	Yes	Yes	T31,T206,T207	Yes	T31,T206,T207	INPUT
cio_tx_o	Yes	Yes	T206,T207,T46	Yes	T206,T207,T46	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T103,T206,T207	Yes	T103,T206,T207	OUTPUT
intr_tx_empty_o	Yes	Yes	T103,T206,T207	Yes	T103,T206,T207	OUTPUT
intr_rx_watermark_o	Yes	Yes	T103,T206,T207	Yes	T103,T206,T207	OUTPUT
intr_tx_done_o	Yes	Yes	T103,T206,T207	Yes	T103,T206,T207	OUTPUT
intr_rx_overflow_o	Yes	Yes	T103,T206,T207	Yes	T103,T206,T207	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T5,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T64,*T74	Yes	T7,T64,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T46	Yes	T75,T76,T46	INPUT
tl_i.a_valid	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	INPUT
tl_o.a_ready	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
tl_o.d_error	Yes	Yes	T71,T77,T119	Yes	T71,T77,T119	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T77,T119	Yes	T71,T77,T119	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T46,*T47,*T71	Yes	T46,T47,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T77,T119	Yes	T71,T72,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T103,*T83,*T136	Yes	T103,T83,T136	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T145,T242	Yes	T78,T145,T242	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T81,T82	Yes	T78,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T81,T82	Yes	T78,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T145,T242	Yes	T78,T145,T242	OUTPUT
cio_rx_i	Yes	Yes	T83,T136,T334	Yes	T83,T136,T334	INPUT
cio_tx_o	Yes	Yes	T83,T136,T334	Yes	T83,T136,T334	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
intr_tx_empty_o	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
intr_rx_watermark_o	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
intr_tx_done_o	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
intr_rx_overflow_o	Yes	Yes	T103,T83,T136	Yes	T103,T83,T136	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T5,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T103,T14,T262	Yes	T103,T14,T262	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T103,T14,T262	Yes	T103,T14,T262	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T64,*T74	Yes	T7,T64,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T46	Yes	T75,T76,T46	INPUT
tl_i.a_valid	Yes	Yes	T103,T14,T145	Yes	T103,T14,T145	INPUT
tl_o.a_ready	Yes	Yes	T103,T14,T145	Yes	T103,T14,T145	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T103,T14,T262	Yes	T103,T14,T262	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T103,T14,T145	Yes	T103,T14,T145	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T103,T14,T145	Yes	T103,T14,T145	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T46,*T47,*T71	Yes	T46,T47,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T103,*T14,*T262	Yes	T103,T14,T262	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T103,T14,T145	Yes	T103,T14,T145	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T78,T145	Yes	T2,T78,T145	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T81,T82	Yes	T78,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T81,T82	Yes	T78,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T78,T145	Yes	T2,T78,T145	OUTPUT
cio_rx_i	Yes	Yes	T14,T262,T84	Yes	T14,T262,T84	INPUT
cio_tx_o	Yes	Yes	T14,T262,T84	Yes	T14,T262,T84	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T103,T14,T262	Yes	T103,T14,T262	OUTPUT
intr_tx_empty_o	Yes	Yes	T103,T14,T262	Yes	T103,T14,T262	OUTPUT
intr_rx_watermark_o	Yes	Yes	T103,T14,T262	Yes	T103,T14,T262	OUTPUT
intr_tx_done_o	Yes	Yes	T103,T14,T262	Yes	T103,T14,T262	OUTPUT
intr_rx_overflow_o	Yes	Yes	T103,T14,T262	Yes	T103,T14,T262	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_break_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_timeout_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T103,T325,T326	Yes	T103,T325,T326	OUTPUT

*Tests covering at least one bit in the range