Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T166,T168,T304
0	1	Covered	T166,T168,T304
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T166,T168,T304
1	Covered	T166,T168,T304

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T166,T168,T304
1	Covered	T166,T168,T304

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T166,T168,T304
1	1	Covered	T166,T168,T304

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T166,T168,T304
1	0	Covered	T166,T168,T304
1	1	Covered	T166,T168,T304

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T166,T168,T304

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T166,T168,T304
0	Covered	T166,T168,T304

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T166,T168,T304
0	Covered	T166,T168,T304

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1050906392	1035421910	0	0
CheckNGreaterZero_A	2046	2046	0	0
GntImpliesReady_A	1050906392	8385	0	0
GntImpliesValid_A	1050906392	8385	0	0
GrantKnown_A	1050906392	1035421910	0	0
IdxKnown_A	1050906392	1035421910	0	0
IndexIsCorrect_A	1050906392	8385	0	0
NoReadyValidNoGrant_A	1050906392	0	0	0
Priority_A	1050906392	8385	0	0
ReadyAndValidImplyGrant_A	1050906392	8385	0	0
ReqAndReadyImplyGrant_A	1050906392	8385	0	0
ReqImpliesValid_A	1050906392	8385	0	0
ValidKnown_A	1050906392	1035421910	0	0
gen_data_port_assertion.DataFlow_A	1050906392	8385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	1035421910	0	0
T1	280164	280054	0	0
T2	464212	464008	0	0
T3	205010	204900	0	0
T4	485092	484866	0	0
T5	213718	213528	0	0
T42	269530	269518	0	0
T60	443394	443146	0	0
T85	1013346	1013222	0	0
T86	200918	200794	0	0
T87	84412	84302	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2046	2046	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T42	2	2	0	0
T60	2	2	0	0
T85	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	8385	0	0
T34	420306	0	0	0
T166	161260	2795	0	0
T168	0	2794	0	0
T201	127396	0	0	0
T216	530614	0	0	0
T268	79464	0	0	0
T304	0	2796	0	0
T307	577418	0	0	0
T402	688692	0	0	0
T403	237706	0	0	0
T404	562894	0	0	0
T405	360050	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	8385	0	0
T34	420306	0	0	0
T166	161260	2795	0	0
T168	0	2794	0	0
T201	127396	0	0	0
T216	530614	0	0	0
T268	79464	0	0	0
T304	0	2796	0	0
T307	577418	0	0	0
T402	688692	0	0	0
T403	237706	0	0	0
T404	562894	0	0	0
T405	360050	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	1035421910	0	0
T1	280164	280054	0	0
T2	464212	464008	0	0
T3	205010	204900	0	0
T4	485092	484866	0	0
T5	213718	213528	0	0
T42	269530	269518	0	0
T60	443394	443146	0	0
T85	1013346	1013222	0	0
T86	200918	200794	0	0
T87	84412	84302	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	1035421910	0	0
T1	280164	280054	0	0
T2	464212	464008	0	0
T3	205010	204900	0	0
T4	485092	484866	0	0
T5	213718	213528	0	0
T42	269530	269518	0	0
T60	443394	443146	0	0
T85	1013346	1013222	0	0
T86	200918	200794	0	0
T87	84412	84302	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	8385	0	0
T34	420306	0	0	0
T166	161260	2795	0	0
T168	0	2794	0	0
T201	127396	0	0	0
T216	530614	0	0	0
T268	79464	0	0	0
T304	0	2796	0	0
T307	577418	0	0	0
T402	688692	0	0	0
T403	237706	0	0	0
T404	562894	0	0	0
T405	360050	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	8385	0	0
T34	420306	0	0	0
T166	161260	2795	0	0
T168	0	2794	0	0
T201	127396	0	0	0
T216	530614	0	0	0
T268	79464	0	0	0
T304	0	2796	0	0
T307	577418	0	0	0
T402	688692	0	0	0
T403	237706	0	0	0
T404	562894	0	0	0
T405	360050	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	8385	0	0
T34	420306	0	0	0
T166	161260	2795	0	0
T168	0	2794	0	0
T201	127396	0	0	0
T216	530614	0	0	0
T268	79464	0	0	0
T304	0	2796	0	0
T307	577418	0	0	0
T402	688692	0	0	0
T403	237706	0	0	0
T404	562894	0	0	0
T405	360050	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	8385	0	0
T34	420306	0	0	0
T166	161260	2795	0	0
T168	0	2794	0	0
T201	127396	0	0	0
T216	530614	0	0	0
T268	79464	0	0	0
T304	0	2796	0	0
T307	577418	0	0	0
T402	688692	0	0	0
T403	237706	0	0	0
T404	562894	0	0	0
T405	360050	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	8385	0	0
T34	420306	0	0	0
T166	161260	2795	0	0
T168	0	2794	0	0
T201	127396	0	0	0
T216	530614	0	0	0
T268	79464	0	0	0
T304	0	2796	0	0
T307	577418	0	0	0
T402	688692	0	0	0
T403	237706	0	0	0
T404	562894	0	0	0
T405	360050	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	1035421910	0	0
T1	280164	280054	0	0
T2	464212	464008	0	0
T3	205010	204900	0	0
T4	485092	484866	0	0
T5	213718	213528	0	0
T42	269530	269518	0	0
T60	443394	443146	0	0
T85	1013346	1013222	0	0
T86	200918	200794	0	0
T87	84412	84302	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050906392	8385	0	0
T34	420306	0	0	0
T166	161260	2795	0	0
T168	0	2794	0	0
T201	127396	0	0	0
T216	530614	0	0	0
T268	79464	0	0	0
T304	0	2796	0	0
T307	577418	0	0	0
T402	688692	0	0	0
T403	237706	0	0	0
T404	562894	0	0	0
T405	360050	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T166,T168,T304
0	1	Covered	T166,T168,T304
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T166,T168,T304
1	Covered	T166,T168,T304

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T166,T168,T304
1	Covered	T166,T168,T304

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T166,T168,T304
1	1	Covered	T166,T168,T304

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T166,T168,T304
1	0	Covered	T166,T168,T304
1	1	Covered	T166,T168,T304

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T166,T168,T304

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T166,T168,T304
0	Covered	T166,T168,T304

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T166,T168,T304
0	Covered	T166,T168,T304

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	525453196	517710955	0	0
CheckNGreaterZero_A	1023	1023	0	0
GntImpliesReady_A	525453196	5195	0	0
GntImpliesValid_A	525453196	5195	0	0
GrantKnown_A	525453196	517710955	0	0
IdxKnown_A	525453196	517710955	0	0
IndexIsCorrect_A	525453196	5195	0	0
NoReadyValidNoGrant_A	525453196	0	0	0
Priority_A	525453196	5195	0	0
ReadyAndValidImplyGrant_A	525453196	5195	0	0
ReqAndReadyImplyGrant_A	525453196	5195	0	0
ReqImpliesValid_A	525453196	5195	0	0
ValidKnown_A	525453196	517710955	0	0
gen_data_port_assertion.DataFlow_A	525453196	5195	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	517710955	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	5195	0	0
T34	210153	0	0	0
T166	80630	1731	0	0
T168	0	1732	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1732	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	5195	0	0
T34	210153	0	0	0
T166	80630	1731	0	0
T168	0	1732	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1732	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	517710955	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	517710955	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	5195	0	0
T34	210153	0	0	0
T166	80630	1731	0	0
T168	0	1732	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1732	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	5195	0	0
T34	210153	0	0	0
T166	80630	1731	0	0
T168	0	1732	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1732	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	5195	0	0
T34	210153	0	0	0
T166	80630	1731	0	0
T168	0	1732	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1732	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	5195	0	0
T34	210153	0	0	0
T166	80630	1731	0	0
T168	0	1732	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1732	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	5195	0	0
T34	210153	0	0	0
T166	80630	1731	0	0
T168	0	1732	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1732	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	517710955	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	5195	0	0
T34	210153	0	0	0
T166	80630	1731	0	0
T168	0	1732	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1732	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T166,T168,T304
0	1	Covered	T166,T168,T304
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T166,T168,T304
1	Covered	T166,T168,T304

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T166,T168,T304
1	Covered	T166,T168,T304

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T166,T168,T304
1	1	Covered	T166,T168,T304

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T166,T168,T304
1	0	Covered	T166,T168,T304
1	1	Covered	T166,T168,T304

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T166,T168,T304

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T166,T168,T304
0	Covered	T166,T168,T304

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T166,T168,T304
0	Covered	T166,T168,T304

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	525453196	517710955	0	0
CheckNGreaterZero_A	1023	1023	0	0
GntImpliesReady_A	525453196	3190	0	0
GntImpliesValid_A	525453196	3190	0	0
GrantKnown_A	525453196	517710955	0	0
IdxKnown_A	525453196	517710955	0	0
IndexIsCorrect_A	525453196	3190	0	0
NoReadyValidNoGrant_A	525453196	0	0	0
Priority_A	525453196	3190	0	0
ReadyAndValidImplyGrant_A	525453196	3190	0	0
ReqAndReadyImplyGrant_A	525453196	3190	0	0
ReqImpliesValid_A	525453196	3190	0	0
ValidKnown_A	525453196	517710955	0	0
gen_data_port_assertion.DataFlow_A	525453196	3190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	517710955	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T42	1	1	0	0
T60	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	3190	0	0
T34	210153	0	0	0
T166	80630	1064	0	0
T168	0	1062	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1064	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	3190	0	0
T34	210153	0	0	0
T166	80630	1064	0	0
T168	0	1062	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1064	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	517710955	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	517710955	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	3190	0	0
T34	210153	0	0	0
T166	80630	1064	0	0
T168	0	1062	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1064	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	3190	0	0
T34	210153	0	0	0
T166	80630	1064	0	0
T168	0	1062	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1064	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	3190	0	0
T34	210153	0	0	0
T166	80630	1064	0	0
T168	0	1062	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1064	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	3190	0	0
T34	210153	0	0	0
T166	80630	1064	0	0
T168	0	1062	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1064	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	3190	0	0
T34	210153	0	0	0
T166	80630	1064	0	0
T168	0	1062	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1064	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	517710955	0	0
T1	140082	140027	0	0
T2	232106	232004	0	0
T3	102505	102450	0	0
T4	242546	242433	0	0
T5	106859	106764	0	0
T42	134765	134759	0	0
T60	221697	221573	0	0
T85	506673	506611	0	0
T86	100459	100397	0	0
T87	42206	42151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525453196	3190	0	0
T34	210153	0	0	0
T166	80630	1064	0	0
T168	0	1062	0	0
T201	63698	0	0	0
T216	265307	0	0	0
T268	39732	0	0	0
T304	0	1064	0	0
T307	288709	0	0	0
T402	344346	0	0	0
T403	118853	0	0	0
T404	281447	0	0	0
T405	180025	0	0	0