Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	80.00	100.00	95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.83	80.00	100.00	98.48

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.83	80.00	100.00	98.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.27	95.32	93.68	95.40		94.44	97.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	95.01	95.25	93.19	95.39		94.22	97.02
u_ast	93.28			93.28
u_padring	99.04	99.21	99.81	96.57		99.60	100.00
u_prim_usb_diff_rx	96.30	100.00	88.89			100.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	857	1	0	0.00
CONT_ASSIGN	870	1	0	0.00
CONT_ASSIGN	899	1	0	0.00
CONT_ASSIGN	907	1	0	0.00
CONT_ASSIGN	914	1	1	100.00
CONT_ASSIGN	917	1	1	100.00
CONT_ASSIGN	923	1	1	100.00
CONT_ASSIGN	925	1	1	100.00
CONT_ASSIGN	929	1	0	0.00
CONT_ASSIGN	932	1	1	100.00
CONT_ASSIGN	1097	1	1	100.00
CONT_ASSIGN	1098	1	1	100.00
CONT_ASSIGN	1099	1	1	100.00
CONT_ASSIGN	1100	1	1	100.00
CONT_ASSIGN	1107	1	1	100.00
CONT_ASSIGN	1124	1	1	100.00
CONT_ASSIGN	1125	1	1	100.00
CONT_ASSIGN	1126	1	1	100.00
CONT_ASSIGN	1127	1	1	100.00
CONT_ASSIGN	1131	1	1	100.00
CONT_ASSIGN	1132	1	1	100.00
CONT_ASSIGN	1133	1	1	100.00
CONT_ASSIGN	1134	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
282	1	1
283	1	1
857	0	1
870	0	1
899	0	1
907	0	1
914	1	1
917	1	1
923	1	1
925	1	1
929	0	1
932	1	1
1097	1	1
1098	1	1
1099	1	1
1100	1	1
1107	1	1
1124	1	1
1125	1	1
1126	1	1
1127	1	1
1131	1	1
1132	1	1
1133	1	1
1134	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T101

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	70	64	91.43
Total Bits	140	134	95.71
Total Bits 0->1	70	70	100.00
Total Bits 1->0	70	64	91.43

Ports	70	64	91.43
Port Bits	140	134	95.71
Port Bits 0->1	70	70	100.00
Port Bits 1->0	70	64	91.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T19,T23,T24	Yes	T19,T23,T24	INOUT
USB_N	Yes	Yes	T19,T23,T24	Yes	T19,T23,T24	INOUT
CC1	No	No		Yes	T8,T9,T10	INOUT
CC2	No	No		Yes	T8,T9,T10	INOUT
FLASH_TEST_VOLT	No	No		Yes	T8,T9,T10	INOUT
FLASH_TEST_MODE0	No	No		Yes	T8,T9,T10	INOUT
FLASH_TEST_MODE1	No	No		Yes	T8,T9,T10	INOUT
OTP_EXT_VOLT	No	No		Yes	T8,T9,T10	INOUT
SPI_HOST_D0	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INOUT
SPI_HOST_D1	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INOUT
SPI_HOST_D2	Yes	Yes	T12,T13,T186	Yes	T12,T13,T186	INOUT
SPI_HOST_D3	Yes	Yes	T12,T13,T186	Yes	T12,T13,T186	INOUT
SPI_HOST_CLK	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INOUT
SPI_HOST_CS_L	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INOUT
SPI_DEV_D0	Yes	Yes	T7,T83,T84	Yes	T7,T83,T84	INOUT
SPI_DEV_D1	Yes	Yes	T7,T83,T84	Yes	T7,T83,T84	INOUT
SPI_DEV_D2	Yes	Yes	T12,T13,T186	Yes	T12,T13,T186	INOUT
SPI_DEV_D3	Yes	Yes	T12,T13,T186	Yes	T12,T13,T186	INOUT
SPI_DEV_CLK	Yes	Yes	T7,T83,T84	Yes	T7,T83,T84	INOUT
SPI_DEV_CS_L	Yes	Yes	T7,T83,T84	Yes	T7,T83,T84	INOUT
IOR8	Yes	Yes	T20,T21,T195	Yes	T20,T21,T195	INOUT
IOR9	Yes	Yes	T20,T21,T22	Yes	T20,T34,T21	INOUT
IOA0	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INOUT
IOA1	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INOUT
IOA2	Yes	Yes	T3,T109,T15	Yes	T3,T109,T15	INOUT
IOA3	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOA4	Yes	Yes	T3,T83,T136	Yes	T3,T83,T136	INOUT
IOA5	Yes	Yes	T3,T83,T136	Yes	T3,T83,T136	INOUT
IOA6	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOA7	Yes	Yes	T3,T205,T15	Yes	T3,T205,T15	INOUT
IOA8	Yes	Yes	T3,T205,T15	Yes	T3,T205,T15	INOUT
IOB0	Yes	Yes	T31,T12,T186	Yes	T31,T12,T186	INOUT
IOB1	Yes	Yes	T31,T12,T186	Yes	T31,T12,T186	INOUT
IOB2	Yes	Yes	T12,T186,T187	Yes	T12,T186,T8	INOUT
IOB3	Yes	Yes	T20,T31,T21	Yes	T20,T31,T21	INOUT
IOB4	Yes	Yes	T31,T206,T207	Yes	T31,T206,T207	INOUT
IOB5	Yes	Yes	T206,T207,T12	Yes	T206,T207,T12	INOUT
IOB6	Yes	Yes	T3,T20,T15	Yes	T3,T20,T15	INOUT
IOB7	Yes	Yes	T3,T16,T17	Yes	T3,T16,T34	INOUT
IOB8	Yes	Yes	T3,T20,T15	Yes	T3,T15,T25	INOUT
IOB9	Yes	Yes	T3,T208,T20	Yes	T3,T208,T15	INOUT
IOB10	Yes	Yes	T3,T208,T109	Yes	T3,T208,T109	INOUT
IOB11	Yes	Yes	T3,T109,T209	Yes	T3,T109,T209	INOUT
IOB12	Yes	Yes	T3,T109,T209	Yes	T3,T109,T209	INOUT
IOC0	Yes	Yes	T42,T6,T7	Yes	T7,T162,T194	INOUT
IOC1	Yes	Yes	T7,T83,T84	Yes	T7,T194,T371	INOUT
IOC2	Yes	Yes	T7,T83,T84	Yes	T7,T194,T371	INOUT
IOC3	Yes	Yes	T210,T211,T212	Yes	T210,T211,T212	INOUT
IOC4	Yes	Yes	T42,T6,T43	Yes	T42,T6,T43	INOUT
IOC5	Yes	Yes	T7,T61,T184	Yes	T7,T64,T61	INOUT
IOC6	Yes	Yes	T5,T45,T44	Yes	T5,T45,T44	INOUT
IOC7	Yes	Yes	T20,T21,T195	Yes	T20,T19,T21	INOUT
IOC8	Yes	Yes	T64,T61,T184	Yes	T7,T61,T213	INOUT
IOC9	Yes	Yes	T3,T20,T34	Yes	T3,T20,T34	INOUT
IOC10	Yes	Yes	T3,T109,T15	Yes	T3,T109,T15	INOUT
IOC11	Yes	Yes	T3,T109,T15	Yes	T3,T109,T15	INOUT
IOC12	Yes	Yes	T3,T109,T15	Yes	T3,T109,T15	INOUT
IOR0	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR1	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR2	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR3	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR4	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR5	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR6	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR7	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR10	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR11	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR12	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR13	Yes	Yes	T3,T16,T17	Yes	T3,T16,T17	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	857	1	0	0.00
CONT_ASSIGN	870	1	0	0.00
CONT_ASSIGN	899	1	0	0.00
CONT_ASSIGN	907	1	0	0.00
CONT_ASSIGN	914	1	1	100.00
CONT_ASSIGN	917	1	1	100.00
CONT_ASSIGN	923	1	1	100.00
CONT_ASSIGN	925	1	1	100.00
CONT_ASSIGN	929	1	0	0.00
CONT_ASSIGN	932	1	1	100.00
CONT_ASSIGN	1097	1	1	100.00
CONT_ASSIGN	1098	1	1	100.00
CONT_ASSIGN	1099	1	1	100.00
CONT_ASSIGN	1100	1	1	100.00
CONT_ASSIGN	1107	1	1	100.00
CONT_ASSIGN	1124	1	1	100.00
CONT_ASSIGN	1125	1	1	100.00
CONT_ASSIGN	1126	1	1	100.00
CONT_ASSIGN	1127	1	1	100.00
CONT_ASSIGN	1131	1	1	100.00
CONT_ASSIGN	1132	1	1	100.00
CONT_ASSIGN	1133	1	1	100.00
CONT_ASSIGN	1134	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
282	1	1
283	1	1
857	0	1
870	0	1
899	0	1
907	0	1
914	1	1
917	1	1
923	1	1
925	1	1
929	0	1
932	1	1
1097	1	1
1098	1	1
1099	1	1
1100	1	1
1107	1	1
1124	1	1
1125	1	1
1126	1	1
1127	1	1
1131	1	1
1132	1	1
1133	1	1
1134	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T101

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	66	64	96.97
Total Bits	132	130	98.48
Total Bits 0->1	66	66	100.00
Total Bits 1->0	66	64	96.97

Ports	66	64	96.97
Port Bits	132	130	98.48
Port Bits 0->1	66	66	100.00
Port Bits 1->0	66	64	96.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T19,T23,T24	Yes	T19,T23,T24	INOUT
USB_N	Yes	Yes	T19,T23,T24	Yes	T19,T23,T24	INOUT
CC1	No	No		Yes	T8,T9,T10	INOUT
CC2	No	No		Yes	T8,T9,T10	INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INOUT
SPI_HOST_D1	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INOUT
SPI_HOST_D2	Yes	Yes	T12,T13,T186	Yes	T12,T13,T186	INOUT
SPI_HOST_D3	Yes	Yes	T12,T13,T186	Yes	T12,T13,T186	INOUT
SPI_HOST_CLK	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INOUT
SPI_HOST_CS_L	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INOUT
SPI_DEV_D0	Yes	Yes	T7,T83,T84	Yes	T7,T83,T84	INOUT
SPI_DEV_D1	Yes	Yes	T7,T83,T84	Yes	T7,T83,T84	INOUT
SPI_DEV_D2	Yes	Yes	T12,T13,T186	Yes	T12,T13,T186	INOUT
SPI_DEV_D3	Yes	Yes	T12,T13,T186	Yes	T12,T13,T186	INOUT
SPI_DEV_CLK	Yes	Yes	T7,T83,T84	Yes	T7,T83,T84	INOUT
SPI_DEV_CS_L	Yes	Yes	T7,T83,T84	Yes	T7,T83,T84	INOUT
IOR8	Yes	Yes	T20,T21,T195	Yes	T20,T21,T195	INOUT
IOR9	Yes	Yes	T20,T21,T22	Yes	T20,T34,T21	INOUT
IOA0	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INOUT
IOA1	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INOUT
IOA2	Yes	Yes	T3,T109,T15	Yes	T3,T109,T15	INOUT
IOA3	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOA4	Yes	Yes	T3,T83,T136	Yes	T3,T83,T136	INOUT
IOA5	Yes	Yes	T3,T83,T136	Yes	T3,T83,T136	INOUT
IOA6	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOA7	Yes	Yes	T3,T205,T15	Yes	T3,T205,T15	INOUT
IOA8	Yes	Yes	T3,T205,T15	Yes	T3,T205,T15	INOUT
IOB0	Yes	Yes	T31,T12,T186	Yes	T31,T12,T186	INOUT
IOB1	Yes	Yes	T31,T12,T186	Yes	T31,T12,T186	INOUT
IOB2	Yes	Yes	T12,T186,T187	Yes	T12,T186,T8	INOUT
IOB3	Yes	Yes	T20,T31,T21	Yes	T20,T31,T21	INOUT
IOB4	Yes	Yes	T31,T206,T207	Yes	T31,T206,T207	INOUT
IOB5	Yes	Yes	T206,T207,T12	Yes	T206,T207,T12	INOUT
IOB6	Yes	Yes	T3,T20,T15	Yes	T3,T20,T15	INOUT
IOB7	Yes	Yes	T3,T16,T17	Yes	T3,T16,T34	INOUT
IOB8	Yes	Yes	T3,T20,T15	Yes	T3,T15,T25	INOUT
IOB9	Yes	Yes	T3,T208,T20	Yes	T3,T208,T15	INOUT
IOB10	Yes	Yes	T3,T208,T109	Yes	T3,T208,T109	INOUT
IOB11	Yes	Yes	T3,T109,T209	Yes	T3,T109,T209	INOUT
IOB12	Yes	Yes	T3,T109,T209	Yes	T3,T109,T209	INOUT
IOC0	Yes	Yes	T42,T6,T7	Yes	T7,T162,T194	INOUT
IOC1	Yes	Yes	T7,T83,T84	Yes	T7,T194,T371	INOUT
IOC2	Yes	Yes	T7,T83,T84	Yes	T7,T194,T371	INOUT
IOC3	Yes	Yes	T210,T211,T212	Yes	T210,T211,T212	INOUT
IOC4	Yes	Yes	T42,T6,T43	Yes	T42,T6,T43	INOUT
IOC5	Yes	Yes	T7,T61,T184	Yes	T7,T64,T61	INOUT
IOC6	Yes	Yes	T5,T45,T44	Yes	T5,T45,T44	INOUT
IOC7	Yes	Yes	T20,T21,T195	Yes	T20,T19,T21	INOUT
IOC8	Yes	Yes	T64,T61,T184	Yes	T7,T61,T213	INOUT
IOC9	Yes	Yes	T3,T20,T34	Yes	T3,T20,T34	INOUT
IOC10	Yes	Yes	T3,T109,T15	Yes	T3,T109,T15	INOUT
IOC11	Yes	Yes	T3,T109,T15	Yes	T3,T109,T15	INOUT
IOC12	Yes	Yes	T3,T109,T15	Yes	T3,T109,T15	INOUT
IOR0	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR1	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR2	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR3	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR4	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INOUT
IOR5	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR6	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR7	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR10	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR11	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR12	Yes	Yes	T3,T15,T25	Yes	T3,T15,T25	INOUT
IOR13	Yes	Yes	T3,T16,T17	Yes	T3,T16,T17	INOUT