Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3958631	1			T73	392		T74	629		T75	3726
values[2]	796273	1			T73	143		T74	219		T75	623
values[3]	116052	1			T73	5		T74	6		T75	1
values[4]	61883	1			T255	306		T545	6		T464	1
values[5]	40881	1			T255	195		T545	6		T464	1
values[6]	29862	1			T255	92		T545	6		T434	15
values[7]	24477	1			T255	42		T545	6		T434	15
values[8]	21289	1			T255	27		T545	6		T434	15
values[9]	18938	1			T255	18		T545	6		T434	15
values[10]	17176	1			T255	44		T545	6		T434	15
values[11]	15782	1			T255	55		T545	6		T434	15
values[12]	14826	1			T255	39		T545	6		T434	15
values[13]	14004	1			T255	32		T545	6		T434	16
values[14]	13121	1			T255	29		T545	6		T434	16
values[15]	12589	1			T255	30		T545	6		T434	15
values[16]	11911	1			T255	27		T545	6		T434	16
values[17]	11083	1			T255	21		T545	6		T434	15
values[18]	10841	1			T255	19		T545	6		T434	15
values[19]	10467	1			T255	21		T545	6		T434	15
values[20]	10472	1			T255	19		T545	6		T434	16
values[21]	10443	1			T255	27		T545	6		T434	15
values[22]	9781	1			T255	16		T545	6		T434	15
values[23]	9419	1			T255	10		T545	6		T434	15
values[24]	9223	1			T255	14		T545	6		T434	15
values[25]	9046	1			T255	14		T545	6		T434	15
values[26]	8588	1			T255	10		T545	6		T434	15
values[27]	8192	1			T255	8		T545	6		T434	15
values[28]	7807	1			T255	8		T545	6		T434	15
values[29]	7321	1			T255	7		T545	6		T434	15
values[30]	6805	1			T255	6		T545	6		T434	16
values[31]	6200	1			T255	10		T545	6		T434	16
values[32]	5810	1			T255	11		T545	6		T434	15
values[33]	5515	1			T255	14		T545	6		T434	15
values[34]	5134	1			T255	13		T545	6		T434	15
values[35]	4886	1			T255	20		T545	6		T434	16
values[36]	4587	1			T255	17		T545	7		T434	15
values[37]	4241	1			T255	17		T545	6		T434	15
values[38]	4134	1			T255	22		T545	6		T434	15
values[39]	4099	1			T255	16		T545	6		T434	16
values[40]	3925	1			T255	9		T545	6		T434	15
values[41]	3798	1			T255	6		T545	6		T434	15
values[42]	3736	1			T255	9		T545	6		T434	16
values[43]	3628	1			T255	15		T545	6		T434	16
values[44]	3563	1			T255	16		T545	6		T434	15
values[45]	3579	1			T255	7		T545	6		T434	15
values[46]	3433	1			T255	11		T545	6		T434	15
values[47]	3409	1			T255	9		T545	6		T434	15
values[48]	3355	1			T255	10		T545	6		T434	15
values[49]	3279	1			T255	6		T545	6		T434	15
values[50]	3157	1			T255	10		T545	6		T434	16
values[51]	3053	1			T255	19		T545	6		T434	16
values[52]	3010	1			T255	8		T545	6		T434	15
values[53]	3000	1			T255	19		T545	6		T434	15
values[54]	2938	1			T255	13		T545	6		T434	15
values[55]	2881	1			T255	7		T545	6		T434	15
values[56]	2808	1			T255	6		T545	6		T434	15
values[57]	2813	1			T255	5		T545	6		T434	15
values[58]	2765	1			T255	7		T545	6		T434	15
values[59]	2722	1			T255	9		T545	6		T434	15
values[60]	2685	1			T255	11		T545	6		T434	15
values[61]	2881	1			T255	12		T545	6		T434	15
values[62]	4452	1			T255	18		T545	6		T434	15
values[63]	12392	1			T255	74		T545	6		T434	15
values[64]	236881	1			T255	262		T545	1080		T434	2796

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	5052845	1			T73	497		T74	513		T75	4014
values[2]	862007	1			T73	100		T74	131		T75	557
values[3]	88397	1			T73	15		T74	19		T75	16
values[4]	15218	1			T74	3		T255	9		T552	2
values[5]	5810	1			T545	9		T464	1		T434	20
values[6]	3736	1			T545	4		T464	1		T434	4
values[7]	2855	1			T545	1		T434	3		T466	1
values[8]	2378	1			T545	1		T434	1		T466	1
values[9]	2010	1			T545	1		T415	3		T523	6
values[10]	1828	1			T415	3		T523	1		T429	3
values[11]	1670	1			T415	4		T429	2		T852	1
values[12]	1515	1			T415	5		T429	2		T852	1
values[13]	1388	1			T415	3		T429	1		T852	1
values[14]	1244	1			T415	2		T429	1		T852	1
values[15]	1186	1			T415	3		T429	2		T852	1
values[16]	1160	1			T415	6		T429	1		T852	1
values[17]	1044	1			T415	3		T429	2		T852	1
values[18]	1005	1			T415	6		T429	4		T852	1
values[19]	883	1			T415	4		T429	1		T852	1
values[20]	927	1			T415	4		T429	2		T852	1
values[21]	946	1			T415	4		T429	8		T852	1
values[22]	885	1			T415	3		T429	3		T852	1
values[23]	830	1			T415	2		T429	1		T852	1
values[24]	777	1			T415	3		T429	5		T852	1
values[25]	714	1			T415	3		T429	4		T852	1
values[26]	716	1			T415	4		T429	2		T852	1
values[27]	657	1			T415	3		T429	3		T852	1
values[28]	679	1			T415	4		T429	1		T852	1
values[29]	684	1			T415	3		T429	1		T852	1
values[30]	609	1			T415	3		T429	2		T852	1
values[31]	639	1			T415	5		T429	1		T852	1
values[32]	643	1			T415	3		T429	4		T852	1
values[33]	645	1			T415	3		T429	2		T852	1
values[34]	586	1			T415	3		T429	2		T852	1
values[35]	549	1			T415	4		T429	1		T852	1
values[36]	527	1			T415	5		T429	1		T852	1
values[37]	545	1			T415	3		T429	4		T852	1
values[38]	527	1			T415	5		T429	2		T852	1
values[39]	528	1			T415	8		T429	1		T852	1
values[40]	572	1			T415	6		T429	1		T852	1
values[41]	535	1			T415	6		T429	2		T852	1
values[42]	475	1			T415	5		T429	1		T852	1
values[43]	458	1			T415	3		T429	1		T852	1
values[44]	478	1			T415	4		T429	1		T852	1
values[45]	438	1			T415	3		T429	2		T852	1
values[46]	463	1			T415	3		T429	1		T852	1
values[47]	478	1			T415	4		T429	3		T852	1
values[48]	486	1			T415	3		T429	7		T852	1
values[49]	442	1			T415	3		T429	3		T852	1
values[50]	445	1			T415	5		T429	3		T852	1
values[51]	449	1			T415	6		T429	2		T852	1
values[52]	395	1			T415	5		T429	3		T852	1
values[53]	403	1			T415	4		T429	1		T852	1
values[54]	398	1			T415	5		T429	1		T852	1
values[55]	403	1			T415	3		T429	1		T852	1
values[56]	445	1			T415	3		T429	2		T852	1
values[57]	410	1			T415	4		T429	1		T852	1
values[58]	428	1			T415	4		T429	1		T852	1
values[59]	413	1			T415	5		T429	1		T852	1
values[60]	419	1			T415	3		T429	1		T852	1
values[61]	478	1			T415	3		T429	1		T852	1
values[62]	844	1			T415	7		T429	1		T852	1
values[63]	3191	1			T415	11		T429	10		T852	1
values[64]	31550	1			T415	189		T429	122		T852	157

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	569376	1			T73	6		T74	11		T75	766
values[2]	2848739	1			T73	258		T74	224		T75	3422
values[3]	1267292	1			T73	172		T74	456		T75	406
values[4]	156658	1			T73	4		T74	13		T463	1
values[5]	81638	1			T463	1		T255	247		T545	6
values[6]	52702	1			T255	219		T545	6		T434	15
values[7]	38441	1			T255	147		T545	6		T434	15
values[8]	30020	1			T255	96		T545	6		T434	15
values[9]	25187	1			T255	104		T545	6		T434	15
values[10]	22153	1			T255	80		T545	6		T434	15
values[11]	19983	1			T255	52		T545	6		T434	15
values[12]	18613	1			T255	34		T545	6		T434	16
values[13]	17227	1			T255	35		T545	6		T434	15
values[14]	16377	1			T255	30		T545	6		T434	15
values[15]	15360	1			T255	21		T545	6		T434	15
values[16]	14609	1			T255	32		T545	6		T434	15
values[17]	14104	1			T255	23		T545	6		T434	17
values[18]	13559	1			T255	18		T545	6		T434	15
values[19]	12908	1			T255	15		T545	6		T434	15
values[20]	12877	1			T255	8		T545	6		T434	15
values[21]	12340	1			T255	8		T545	7		T434	15
values[22]	11454	1			T255	6		T545	6		T434	15
values[23]	11114	1			T255	12		T545	6		T434	15
values[24]	10490	1			T255	12		T545	6		T434	15
values[25]	10105	1			T255	19		T545	6		T434	15
values[26]	9422	1			T255	13		T545	7		T434	15
values[27]	9054	1			T255	15		T545	6		T434	15
values[28]	8647	1			T255	9		T545	6		T434	15
values[29]	8088	1			T255	12		T545	7		T434	16
values[30]	7534	1			T255	6		T545	6		T434	15
values[31]	6894	1			T255	6		T545	6		T434	15
values[32]	6523	1			T255	11		T545	6		T434	15
values[33]	6290	1			T255	11		T545	6		T434	15
values[34]	5895	1			T255	9		T545	6		T434	15
values[35]	5341	1			T255	7		T545	6		T434	15
values[36]	5104	1			T255	10		T545	6		T434	15
values[37]	4910	1			T255	14		T545	6		T434	15
values[38]	4582	1			T255	8		T545	6		T434	15
values[39]	4519	1			T255	10		T545	6		T434	15
values[40]	4216	1			T255	8		T545	6		T434	15
values[41]	4029	1			T255	12		T545	6		T434	15
values[42]	3838	1			T255	14		T545	6		T434	15
values[43]	3888	1			T255	18		T545	6		T434	15
values[44]	3914	1			T255	9		T545	6		T434	16
values[45]	3778	1			T255	12		T545	6		T434	15
values[46]	3753	1			T255	7		T545	6		T434	15
values[47]	3667	1			T255	9		T545	6		T434	15
values[48]	3634	1			T255	6		T545	6		T434	15
values[49]	3542	1			T255	8		T545	6		T434	15
values[50]	3595	1			T255	10		T545	6		T434	15
values[51]	3497	1			T255	17		T545	6		T434	15
values[52]	3311	1			T255	17		T545	6		T434	15
values[53]	3250	1			T255	9		T545	6		T434	15
values[54]	3222	1			T255	8		T545	6		T434	15
values[55]	3317	1			T255	7		T545	6		T434	15
values[56]	3151	1			T255	5		T545	6		T434	17
values[57]	3176	1			T255	8		T545	6		T434	15
values[58]	3055	1			T255	7		T545	6		T434	16
values[59]	3156	1			T255	7		T545	6		T434	15
values[60]	3150	1			T255	10		T545	6		T434	16
values[61]	3176	1			T255	9		T545	6		T434	15
values[62]	4417	1			T255	21		T545	6		T434	15
values[63]	10913	1			T255	54		T545	7		T434	15
values[64]	229194	1			T255	158		T545	1160		T434	2687