Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2057003	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38755580

1

T1

49651

T2

7458

T3

3314

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28572729	1			T1	19658		T2	3373		T3	733
values[0x0]	10698517	1			T1	29993		T2	4085		T3	2581
values[0x1]	1541337	1			T1	2795		T2	361		T3	95

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	664051	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40148532

1

T1

52446

T2

7819

T3

3409

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19229804	1			T1	26225		T2	3910		T3	1705
valid_sources[0x01]	19228375	1			T1	26221		T2	3909		T3	1704
valid_sources[0x02]	38124	1			T208	1		T385	240		T557	8
valid_sources[0x03]	37467	1			T68	2		T385	254		T557	8
valid_sources[0x04]	41680	1			T385	216		T557	13		T907	6
valid_sources[0x05]	38040	1			T68	1		T78	3		T208	1
valid_sources[0x06]	38005	1			T208	1		T385	216		T557	11
valid_sources[0x07]	38193	1			T385	279		T557	11		T907	6
valid_sources[0x08]	37927	1			T68	6		T77	7		T78	2
valid_sources[0x09]	37413	1			T78	1		T385	230		T557	10
valid_sources[0x0a]	38144	1			T385	235		T557	4		T907	12
valid_sources[0x0b]	38019	1			T385	214		T557	7		T907	5
valid_sources[0x0c]	37976	1			T77	4		T78	1		T385	260
valid_sources[0x0d]	38099	1			T208	1		T385	251		T557	10
valid_sources[0x0e]	37493	1			T68	2		T77	2		T385	271
valid_sources[0x0f]	38732	1			T68	1		T78	1		T49	39
valid_sources[0x10]	38325	1			T78	2		T385	269		T557	10
valid_sources[0x11]	38093	1			T208	2		T385	247		T557	12
valid_sources[0x12]	37563	1			T68	1		T77	6		T385	238
valid_sources[0x13]	37039	1			T78	3		T385	238		T557	13
valid_sources[0x14]	37853	1			T208	3		T385	243		T557	19
valid_sources[0x15]	37424	1			T68	2		T385	244		T557	10
valid_sources[0x16]	38107	1			T68	1		T78	2		T385	255
valid_sources[0x17]	37822	1			T208	2		T385	251		T557	11
valid_sources[0x18]	37235	1			T77	5		T208	2		T86	39
valid_sources[0x19]	37577	1			T208	1		T385	241		T557	15
valid_sources[0x1a]	37197	1			T78	4		T208	1		T385	258
valid_sources[0x1b]	37475	1			T68	2		T208	2		T385	216
valid_sources[0x1c]	39272	1			T385	240		T557	13		T907	7
valid_sources[0x1d]	37804	1			T208	1		T385	233		T557	7
valid_sources[0x1e]	37720	1			T208	1		T385	281		T557	13
valid_sources[0x1f]	37340	1			T385	236		T557	8		T907	7
valid_sources[0x20]	38378	1			T68	2		T77	1		T208	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27848329

1

T1

19658

T2

3373

T3

733

values[0x0]

all_enables

biggest_size

10646377

1

T1

29993

T2

4085

T3

2581

values[0x1]

all_enables

biggest_size

260874

1

T68

25

T77

16

T78

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3023290	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

479026

1

T73

84

T74

6

T75

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1187271	1			T73	157		T74	24		T75	92
values[0x0]	1130037	1			T73	199		T74	5		T75	21
values[0x1]	1185008	1			T73	184		T74	15		T75	93

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2339619	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1162697

1

T73

175

T74

21

T75

81

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53718	1			T73	6		T74	1		T75	2
valid_sources[0x01]	54466	1			T73	3		T74	2		T75	1
valid_sources[0x02]	55123	1			T73	14		T75	4		T152	5
valid_sources[0x03]	54031	1			T73	6		T152	35		T463	3
valid_sources[0x04]	55487	1			T73	14		T75	2		T152	37
valid_sources[0x05]	55457	1			T73	13		T74	3		T75	4
valid_sources[0x06]	54724	1			T73	3		T75	9		T152	13
valid_sources[0x07]	54895	1			T73	17		T74	3		T75	5
valid_sources[0x08]	53983	1			T73	11		T75	3		T463	4
valid_sources[0x09]	53931	1			T73	7		T74	1		T75	3
valid_sources[0x0a]	54652	1			T73	7		T75	2		T463	11
valid_sources[0x0b]	54348	1			T73	5		T75	2		T152	8
valid_sources[0x0c]	55383	1			T73	5		T75	4		T152	6
valid_sources[0x0d]	56730	1			T73	17		T74	1		T75	3
valid_sources[0x0e]	54640	1			T73	8		T74	1		T75	1
valid_sources[0x0f]	55606	1			T73	10		T463	2		T255	13
valid_sources[0x10]	55632	1			T73	6		T74	2		T75	1
valid_sources[0x11]	55235	1			T73	5		T74	2		T75	3
valid_sources[0x12]	54256	1			T73	8		T75	1		T152	35
valid_sources[0x13]	54205	1			T73	8		T74	1		T75	5
valid_sources[0x14]	54441	1			T73	14		T74	2		T75	2
valid_sources[0x15]	54252	1			T73	14		T74	2		T75	3
valid_sources[0x16]	55294	1			T73	10		T75	8		T152	13
valid_sources[0x17]	54405	1			T73	9		T74	1		T75	2
valid_sources[0x18]	54562	1			T73	5		T74	1		T75	2
valid_sources[0x19]	55278	1			T73	6		T75	1		T463	6
valid_sources[0x1a]	54634	1			T73	10		T74	1		T75	2
valid_sources[0x1b]	53224	1			T73	9		T75	3		T463	7
valid_sources[0x1c]	55378	1			T73	11		T75	1		T463	25
valid_sources[0x1d]	54193	1			T73	5		T74	1		T75	2
valid_sources[0x1e]	54320	1			T73	12		T75	2		T152	54
valid_sources[0x1f]	54607	1			T73	7		T74	1		T75	3
valid_sources[0x20]	54005	1			T73	9		T75	4		T152	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50522

1

T73

6

T74

2

T75

7

values[0x0]

all_enables

biggest_size

378133

1

T73

67

T74

3

T75

14

values[0x1]

all_enables

biggest_size

50371

1

T73

11

T74

1

T75

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3223109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

526515

1

T73

97

T74

3

T75

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1282161	1			T73	184		T74	13		T75	95
values[0x0]	1183523	1			T73	217		T74	1		T75	15
values[0x1]	1283940	1			T73	211		T74	13		T75	104

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2473385	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1276239

1

T73

219

T74

11

T75

77

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58591	1			T75	1		T463	2		T255	11
valid_sources[0x01]	58782	1			T74	1		T75	4		T152	16
valid_sources[0x02]	58570	1			T73	3		T75	5		T152	9
valid_sources[0x03]	59571	1			T73	6		T74	1		T75	5
valid_sources[0x04]	58537	1			T73	9		T75	2		T152	29
valid_sources[0x05]	59111	1			T73	15		T74	1		T152	6
valid_sources[0x06]	58413	1			T73	13		T74	2		T75	4
valid_sources[0x07]	59262	1			T73	5		T75	3		T463	2
valid_sources[0x08]	58448	1			T73	28		T74	1		T75	4
valid_sources[0x09]	57831	1			T73	26		T74	1		T75	2
valid_sources[0x0a]	57802	1			T73	24		T75	3		T255	15
valid_sources[0x0b]	58602	1			T73	14		T74	1		T75	5
valid_sources[0x0c]	58436	1			T75	3		T152	8		T255	3
valid_sources[0x0d]	60665	1			T75	2		T255	7		T552	1
valid_sources[0x0e]	59127	1			T73	25		T75	1		T152	33
valid_sources[0x0f]	58748	1			T73	9		T75	1		T255	3
valid_sources[0x10]	58860	1			T75	2		T152	33		T255	8
valid_sources[0x11]	58023	1			T73	3		T75	3		T463	2
valid_sources[0x12]	57568	1			T73	4		T75	2		T152	26
valid_sources[0x13]	58694	1			T75	2		T463	2		T255	7
valid_sources[0x14]	58131	1			T73	16		T75	3		T152	13
valid_sources[0x15]	59438	1			T73	1		T74	1		T75	5
valid_sources[0x16]	58806	1			T75	4		T152	10		T463	1
valid_sources[0x17]	58848	1			T75	3		T152	16		T255	13
valid_sources[0x18]	59264	1			T74	1		T152	22		T463	1
valid_sources[0x19]	58572	1			T73	24		T75	2		T463	1
valid_sources[0x1a]	58715	1			T73	9		T74	1		T75	4
valid_sources[0x1b]	58097	1			T75	2		T463	2		T255	8
valid_sources[0x1c]	58888	1			T73	12		T74	2		T463	1
valid_sources[0x1d]	58682	1			T73	20		T75	6		T152	9
valid_sources[0x1e]	58841	1			T75	6		T152	58		T255	5
valid_sources[0x1f]	58135	1			T75	3		T152	11		T255	9
valid_sources[0x20]	57214	1			T73	18		T74	1		T75	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

55060

1

T73

8

T75

6

T152

13

values[0x0]

all_enables

biggest_size

416196

1

T73

78

T74

1

T75

5

values[0x1]

all_enables

biggest_size

55259

1

T73

11

T74

2

T75

8

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3047540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

482283

1

T73

62

T74

3

T75

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1196647	1			T73	142		T74	11		T75	98
values[0x0]	1138720	1			T73	142		T74	2		T75	17
values[0x1]	1194456	1			T73	156		T74	15		T75	88

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2358023	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1171800

1

T73

145

T74

8

T75

75

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55212	1			T73	10		T75	3		T255	9
valid_sources[0x01]	54602	1			T73	14		T75	5		T152	15
valid_sources[0x02]	55366	1			T73	9		T75	3		T152	13
valid_sources[0x03]	54819	1			T73	5		T74	1		T75	2
valid_sources[0x04]	55942	1			T73	13		T75	4		T152	46
valid_sources[0x05]	54918	1			T73	7		T75	2		T152	18
valid_sources[0x06]	55716	1			T73	9		T74	1		T75	6
valid_sources[0x07]	55169	1			T73	3		T75	2		T255	11
valid_sources[0x08]	55322	1			T73	7		T74	1		T75	2
valid_sources[0x09]	55715	1			T73	6		T74	2		T75	2
valid_sources[0x0a]	54635	1			T73	7		T74	1		T75	2
valid_sources[0x0b]	54896	1			T73	5		T74	1		T75	3
valid_sources[0x0c]	56145	1			T73	5		T74	1		T75	5
valid_sources[0x0d]	55972	1			T73	12		T75	5		T463	7
valid_sources[0x0e]	54867	1			T73	12		T74	1		T75	4
valid_sources[0x0f]	56029	1			T73	10		T74	1		T75	2
valid_sources[0x10]	55706	1			T73	5		T74	1		T75	6
valid_sources[0x11]	55340	1			T73	4		T75	2		T255	6
valid_sources[0x12]	54900	1			T73	6		T75	6		T152	21
valid_sources[0x13]	54832	1			T73	9		T75	2		T255	12
valid_sources[0x14]	55367	1			T73	7		T75	3		T152	20
valid_sources[0x15]	54776	1			T73	10		T75	1		T152	12
valid_sources[0x16]	55035	1			T73	6		T75	3		T152	11
valid_sources[0x17]	55754	1			T73	5		T75	5		T152	17
valid_sources[0x18]	54716	1			T73	5		T75	1		T152	29
valid_sources[0x19]	54882	1			T73	5		T74	1		T75	6
valid_sources[0x1a]	55144	1			T73	5		T74	1		T75	2
valid_sources[0x1b]	54546	1			T73	1		T75	3		T463	2
valid_sources[0x1c]	55037	1			T73	4		T74	1		T75	4
valid_sources[0x1d]	55158	1			T73	9		T74	2		T75	7
valid_sources[0x1e]	54873	1			T73	10		T74	1		T75	5
valid_sources[0x1f]	55061	1			T73	6		T75	2		T152	15
valid_sources[0x20]	54722	1			T73	4		T152	33		T463	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50955

1

T73

10

T74

1

T75

8

values[0x0]

all_enables

biggest_size

380738

1

T73

48

T75

6

T152

94

values[0x1]

all_enables

biggest_size

50590

1

T73

4

T74

2

T75

7