Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	542908481	63179194	0	0
DepthKnown_A	542908481	542800654	0	0
RvalidKnown_A	542908481	542800654	0	0
WreadyKnown_A	542908481	542800654	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	63179194	0	0
T1	111859	123855	0	0
T2	143320	19368	0	0
T3	73250	7998	0	0
T4	137717	19083	0	0
T5	200368	17733	0	0
T6	756597	486661	0	0
T44	130172	143721	0	0
T45	795430	702554	0	0
T88	667300	59822	0	0
T89	88544	10517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	542908481	49159714	0	0
DepthKnown_A	542908481	542800654	0	0
RvalidKnown_A	542908481	542800654	0	0
WreadyKnown_A	542908481	542800654	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	49159714	0	0
T1	111859	91744	0	0
T2	143320	14192	0	0
T3	73250	5622	0	0
T4	137717	13808	0	0
T5	200368	13976	0	0
T6	756597	480939	0	0
T44	130172	124283	0	0
T45	795430	295873	0	0
T88	667300	55845	0	0
T89	88544	7998	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	542908481	45257820	0	0
DepthKnown_A	542908481	542800654	0	0
RvalidKnown_A	542908481	542800654	0	0
WreadyKnown_A	542908481	542800654	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	45257820	0	0
T1	111859	53975	0	0
T2	143320	8097	0	0
T3	73250	3555	0	0
T4	137717	7750	0	0
T5	200368	10645	0	0
T6	756597	544916	0	0
T44	130172	190533	0	0
T45	795430	221625	0	0
T88	667300	72066	0	0
T89	88544	5705	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	542908481	38460634	0	0
DepthKnown_A	542908481	542800654	0	0
RvalidKnown_A	542908481	542800654	0	0
WreadyKnown_A	542908481	542800654	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	38460634	0	0
T1	111859	52446	0	0
T2	143320	7819	0	0
T3	73250	3409	0	0
T4	137717	7475	0	0
T5	200368	10348	0	0
T6	756597	543562	0	0
T44	130172	116749	0	0
T45	795430	58295	0	0
T88	667300	71861	0	0
T89	88544	5546	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542908481	542800654	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	626374713	96058	0	0
DepthKnown_A	626374713	626250622	0	0
RvalidKnown_A	626374713	626250622	0	0
WreadyKnown_A	626374713	626250622	0	0
gen_passthru_fifo.paramCheckPass	2939	2939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	96058	0	0
T1	111859	218	0	0
T2	143320	26	0	0
T3	73250	13	0	0
T4	137717	26	0	0
T5	200368	27	0	0
T6	756597	60	0	0
T44	130172	34	0	0
T45	795430	2	0	0
T88	667300	53	0	0
T89	88544	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2939	2939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	626374713	98650	0	0
DepthKnown_A	626374713	626250622	0	0
RvalidKnown_A	626374713	626250622	0	0
WreadyKnown_A	626374713	626250622	0	0
gen_passthru_fifo.paramCheckPass	2939	2939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	98650	0	0
T1	111859	218	0	0
T2	143320	26	0	0
T3	73250	13	0	0
T4	137717	26	0	0
T5	200368	27	0	0
T6	756597	60	0	0
T44	130172	34	0	0
T45	795430	2	0	0
T88	667300	53	0	0
T89	88544	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2939	2939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	626374713	52529	0	0
DepthKnown_A	626374713	626250622	0	0
RvalidKnown_A	626374713	626250622	0	0
WreadyKnown_A	626374713	626250622	0	0
gen_passthru_fifo.paramCheckPass	2939	2939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	52529	0	0
T1	111859	191	0	0
T2	143320	23	0	0
T3	73250	12	0	0
T4	137717	23	0	0
T5	200368	25	0	0
T6	756597	58	0	0
T44	130172	5	0	0
T45	795430	1	0	0
T88	667300	52	0	0
T89	88544	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2939	2939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	626374713	52529	0	0
DepthKnown_A	626374713	626250622	0	0
RvalidKnown_A	626374713	626250622	0	0
WreadyKnown_A	626374713	626250622	0	0
gen_passthru_fifo.paramCheckPass	2939	2939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	52529	0	0
T1	111859	191	0	0
T2	143320	23	0	0
T3	73250	12	0	0
T4	137717	23	0	0
T5	200368	25	0	0
T6	756597	58	0	0
T44	130172	5	0	0
T45	795430	1	0	0
T88	667300	52	0	0
T89	88544	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2939	2939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	626374713	43529	0	0
DepthKnown_A	626374713	626250622	0	0
RvalidKnown_A	626374713	626250622	0	0
WreadyKnown_A	626374713	626250622	0	0
gen_passthru_fifo.paramCheckPass	2939	2939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	43529	0	0
T1	111859	27	0	0
T2	143320	3	0	0
T3	73250	1	0	0
T4	137717	3	0	0
T5	200368	2	0	0
T6	756597	2	0	0
T44	130172	29	0	0
T45	795430	1	0	0
T88	667300	1	0	0
T89	88544	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2939	2939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	626374713	46121	0	0
DepthKnown_A	626374713	626250622	0	0
RvalidKnown_A	626374713	626250622	0	0
WreadyKnown_A	626374713	626250622	0	0
gen_passthru_fifo.paramCheckPass	2939	2939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	46121	0	0
T1	111859	27	0	0
T2	143320	3	0	0
T3	73250	1	0	0
T4	137717	3	0	0
T5	200368	2	0	0
T6	756597	2	0	0
T44	130172	29	0	0
T45	795430	1	0	0
T88	667300	1	0	0
T89	88544	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626374713	626250622	0	0
T1	111859	111798	0	0
T2	143320	143265	0	0
T3	73250	73195	0	0
T4	137717	137666	0	0
T5	200368	200201	0	0
T6	756597	756585	0	0
T44	130172	130166	0	0
T45	795430	795379	0	0
T88	667300	667249	0	0
T89	88544	88482	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2939	2939	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0