Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T44,T45,T88	Yes	T44,T45,T88	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T44,T45,T88	Yes	T44,T45,T88	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T68,*T76	Yes	T45,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T44,T45,T88	Yes	T44,T45,T88	INPUT
tl_o.a_ready	Yes	Yes	T44,T45,T88	Yes	T44,T45,T88	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T44,T88,T6	Yes	T44,T88,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T44,T45,T88	Yes	T44,T45,T88	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T44,T45,T88	Yes	T44,T45,T88	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T45,*T262,*T263	Yes	T45,T262,T263	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T44,*T45,*T88	Yes	T44,T45,T88	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T44,T45,T88	Yes	T44,T45,T88	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T265,T156,T759	Yes	T265,T156,T759	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T143,T247,T82	Yes	T247,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T247,T82,T83	Yes	T143,T247,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T265,T156,T759	Yes	T265,T156,T759	OUTPUT
cio_rx_i	Yes	Yes	T1,T5,T88	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T44,T45,T88	Yes	T44,T45,T88	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T88,T6,T218	Yes	T88,T6,T218	OUTPUT
intr_tx_empty_o	Yes	Yes	T88,T6,T218	Yes	T88,T6,T218	OUTPUT
intr_rx_watermark_o	Yes	Yes	T88,T6,T218	Yes	T88,T6,T218	OUTPUT
intr_tx_done_o	Yes	Yes	T88,T6,T218	Yes	T88,T6,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T88,T6,T218	Yes	T88,T6,T218	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_break_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_timeout_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T44,T45,T6	Yes	T44,T45,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T44,T45,T6	Yes	T44,T45,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T68,*T76	Yes	T45,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T44,T45,T6	Yes	T44,T45,T6	INPUT
tl_o.a_ready	Yes	Yes	T44,T45,T6	Yes	T44,T45,T6	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T44,T6,T7	Yes	T44,T6,T7	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T44,T45,T6	Yes	T44,T45,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T44,T45,T6	Yes	T44,T45,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T45,*T262,*T263	Yes	T45,T262,T263	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T44,*T45,*T6	Yes	T44,T45,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T44,T45,T6	Yes	T44,T45,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T156,T760,T761	Yes	T156,T760,T761	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T156,T760,T761	Yes	T156,T760,T761	OUTPUT
cio_rx_i	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T44,T45,T6	Yes	T44,T45,T6	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T6,T221,T108	Yes	T6,T221,T108	OUTPUT
intr_tx_empty_o	Yes	Yes	T6,T221,T108	Yes	T6,T221,T108	OUTPUT
intr_rx_watermark_o	Yes	Yes	T6,T221,T108	Yes	T6,T221,T108	OUTPUT
intr_tx_done_o	Yes	Yes	T6,T221,T108	Yes	T6,T221,T108	OUTPUT
intr_rx_overflow_o	Yes	Yes	T6,T221,T108	Yes	T6,T221,T108	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_break_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_timeout_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T68,*T76	Yes	T45,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T88,T156,T218	Yes	T88,T156,T218	INPUT
tl_o.a_ready	Yes	Yes	T88,T156,T218	Yes	T88,T156,T218	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T88,T156,T218	Yes	T88,T156,T218	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T88,T156,T218	Yes	T88,T156,T218	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T86,*T49	Yes	T77,T86,T49	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T88,*T218,*T219	Yes	T88,T218,T219	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T88,T156,T218	Yes	T88,T156,T218	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T265,T156,T759	Yes	T265,T156,T759	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T265,T156,T759	Yes	T265,T156,T759	OUTPUT
cio_rx_i	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	INPUT
cio_tx_o	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	OUTPUT
intr_tx_empty_o	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	OUTPUT
intr_rx_watermark_o	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	OUTPUT
intr_tx_done_o	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	OUTPUT
intr_rx_overflow_o	Yes	Yes	T88,T218,T219	Yes	T88,T218,T219	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_break_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_timeout_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T142,T332	Yes	T11,T142,T332	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T142,T332	Yes	T11,T142,T332	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T68,*T76	Yes	T45,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T156,T11,T142	Yes	T156,T11,T142	INPUT
tl_o.a_ready	Yes	Yes	T156,T11,T142	Yes	T156,T11,T142	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T142,T332	Yes	T11,T142,T332	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T156,T11,T142	Yes	T156,T11,T142	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T156,T11,T142	Yes	T156,T11,T142	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T86,*T49	Yes	T77,T86,T49	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T142,*T332	Yes	T11,T142,T332	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T156,T11,T142	Yes	T156,T11,T142	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T156,T50,T328	Yes	T156,T50,T328	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T156,T50,T328	Yes	T156,T50,T328	OUTPUT
cio_rx_i	Yes	Yes	T142,T332,T333	Yes	T142,T332,T333	INPUT
cio_tx_o	Yes	Yes	T142,T332,T333	Yes	T142,T332,T333	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T142,T332,T321	Yes	T142,T332,T321	OUTPUT
intr_tx_empty_o	Yes	Yes	T142,T332,T321	Yes	T142,T332,T321	OUTPUT
intr_rx_watermark_o	Yes	Yes	T142,T332,T321	Yes	T142,T332,T321	OUTPUT
intr_tx_done_o	Yes	Yes	T142,T332,T321	Yes	T142,T332,T321	OUTPUT
intr_rx_overflow_o	Yes	Yes	T142,T332,T321	Yes	T142,T332,T321	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_break_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_timeout_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T11	Yes	T14,T15,T11	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T11	Yes	T14,T15,T11	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T68,*T76	Yes	T45,T68,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T156,T14,T15	Yes	T156,T14,T15	INPUT
tl_o.a_ready	Yes	Yes	T156,T14,T15	Yes	T156,T14,T15	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T11	Yes	T14,T15,T11	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T156,T14,T15	Yes	T156,T14,T15	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T156,T14,T15	Yes	T156,T14,T15	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T86,*T49	Yes	T77,T86,T49	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T11	Yes	T14,T15,T11	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T156,T14,T15	Yes	T156,T14,T15	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T156,T143,T540	Yes	T156,T143,T540	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T143,T247,T82	Yes	T247,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T247,T82,T83	Yes	T143,T247,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T156,T143,T540	Yes	T156,T143,T540	OUTPUT
cio_rx_i	Yes	Yes	T14,T15,T87	Yes	T14,T15,T87	INPUT
cio_tx_o	Yes	Yes	T14,T15,T87	Yes	T14,T15,T87	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T15,T87	Yes	T14,T15,T87	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T15,T87	Yes	T14,T15,T87	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T15,T87	Yes	T14,T15,T87	OUTPUT
intr_tx_done_o	Yes	Yes	T14,T15,T87	Yes	T14,T15,T87	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T15,T87	Yes	T14,T15,T87	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_break_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_timeout_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T321,T322,T323	Yes	T321,T322,T323	OUTPUT

*Tests covering at least one bit in the range