Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T74,T75,T255	Yes	T74,T75,T255	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T45,T7,T223	Yes	T45,T7,T223	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T45,T7,T223	Yes	T45,T7,T223	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T78,T74,T75	Yes	T78,T74,T75	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T78,T73,T74	Yes	T78,T73,T74	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T1,T45,T7	Yes	T1,T45,T7	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T45,T68,T69	Yes	T45,T68,T69	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T45,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T45,T68,T69	Yes	T45,T68,T69	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T45,T68,T69	Yes	T45,T68,T69	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T45,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T45,T68,T69	Yes	T45,T68,T69	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T45,T68,T69	Yes	T45,T68,T69	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T45,*T68,*T69	Yes	T45,T68,T69	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T45,T68,T69	Yes	T45,T68,T69	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T45,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T45,T76,T261	Yes	T45,T76,T261	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T76,T261	Yes	T45,T76,T261	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T45,T76,T261	Yes	T45,T76,T261	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T45,T76,T261	Yes	T45,T76,T261	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T45,T76,T261	Yes	T45,T76,T261	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T45,*T76,*T261	Yes	T45,T76,T261	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T45,T76,T261	Yes	T45,T76,T261	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T45,T5	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T45,T76,T261	Yes	T45,T76,T261	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T76,T261	Yes	T45,T76,T261	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T45,T5	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T45,*T76,*T261	Yes	T45,T76,T261	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T45,T5	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T45,T76,T261	Yes	T45,T76,T261	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T44,T7,T68	Yes	T44,T7,T68	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T50,T51,T52	Yes	T50,T51,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T401,T268,T402	Yes	T401,T268,T402	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T401,T268,T402	Yes	T401,T268,T402	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T50,T51,T52	Yes	T50,T51,T52	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T401,T268,T402	Yes	T401,T268,T402	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T401,T268,T402	Yes	T401,T268,T402	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T401,T268,T402	Yes	T401,T268,T402	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T401,T402,T403	Yes	T401,T402,T403	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T50,T51,T52	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T401,T402,T403	Yes	T401,T402,T403	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T73,T74,*T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T268,*T402,*T404	Yes	T401,T268,T402	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T401,T268,T402	Yes	T401,T268,T402	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T45,*T68,*T76	Yes	T45,T68,T76	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T62,T223,T393	Yes	T62,T223,T393	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T45,*T68,*T76	Yes	T45,T68,T76	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T74	Yes	T77,T73,T74	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T12,T205,T207	Yes	T12,T205,T207	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T157,T11,T12	Yes	T157,T11,T12	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T157,T11,T12	Yes	T157,T11,T12	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T77,*T73,*T74	Yes	T77,T73,T74	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T157,*T11,*T12	Yes	T157,T11,T12	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T156,T157,T11	Yes	T156,T157,T11	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T74	Yes	T77,T73,T74	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T77,*T73,*T74	Yes	T77,T73,T74	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T157,*T11,*T388	Yes	T157,T11,T388	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T157,T11,T388	Yes	T157,T11,T388	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T77,*T86,*T49	Yes	T77,T86,T49	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_usbdev_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T19,T20,T72	Yes	T19,T20,T72	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T20,T394	Yes	T19,T20,T394	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T18,T19,T20	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T77,*T86,*T49	Yes	T77,T86,T49	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T17,*T18,*T19	Yes	T18,T19,T20	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T44,T5	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T86,T73,T74	Yes	T86,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T86,T73,T74	Yes	T86,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T86,T73,T74	Yes	T86,T73,T74	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T44	Yes	T1,T2,T44	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T44,T5	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T111,T741,T742	Yes	T111,T741,T742	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	INPUT
tl_hmac_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	INPUT
tl_hmac_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T44,*T7,*T42	Yes	T44,T7,T42	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T44,T7,T42	Yes	T44,T7,T42	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T86,*T49,*T73	Yes	T86,T49,T73	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T89,T378,T460	Yes	T89,T378,T460	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	INPUT
tl_kmac_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T89,T123,T378	Yes	T89,T378,T157	INPUT
tl_kmac_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T86,*T49,*T73	Yes	T86,T49,T73	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T89,*T123,*T378	Yes	T89,T378,T157	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T89,T123,T378	Yes	T89,T123,T378	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	INPUT
tl_aes_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T3,T379,T106	Yes	T3,T379,T125	INPUT
tl_aes_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T3,*T379,*T125	Yes	T3,T379,T125	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T3,T379,T125	Yes	T3,T379,T125	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T44,T5	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T44,T5	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T123,*T7,*T124	Yes	T44,T123,T7	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T123,*T124,*T125	Yes	T123,T124,T125	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T123,*T124,*T125	Yes	T123,T124,T125	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	INPUT
tl_edn1_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	INPUT
tl_edn1_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T123,*T124,*T125	Yes	T123,T124,T125	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T77,*T73,*T74	Yes	T77,T73,T74	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T77,*T73,*T74	Yes	T77,T73,T74	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T44,T5	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T68,*T78,*T208	Yes	T68,T78,T208	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	INPUT
tl_otbn_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	INPUT
tl_otbn_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T68,*T78,*T208	Yes	T68,T78,T208	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T44,*T7,*T157	Yes	T44,T7,T157	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T44,T7,T157	Yes	T44,T7,T157	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T44,T5	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T44,T123,T7	Yes	T44,T123,T7	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T123,T7	Yes	T44,T123,T7	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T44,T123,T7	Yes	T44,T123,T7	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T44,T123,T46	Yes	T44,T123,T46	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T44,T123,T7	Yes	T44,T123,T7	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T44,T123,T7	Yes	T44,T123,T7	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T44,T123,T7	Yes	T44,T123,T7	INPUT
tl_keymgr_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T44,T123,T46	Yes	T44,T123,T46	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T123,T7	Yes	T44,T123,T7	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T44,T123,T7	Yes	T44,T123,T7	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T86,*T73,*T74	Yes	T86,T73,T74	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T44,*T123,*T7	Yes	T44,T123,T7	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T44,T123,T7	Yes	T44,T123,T7	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T262,*T263,*T73	Yes	T262,T263,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T74,T75,T152	Yes	T74,T75,T152	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T44	Yes	T1,T2,T44	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T44	Yes	T1,T2,T44	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T262,T263,T73	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T44,T45	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T44,T45,T7	Yes	T44,T45,T7	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T45,T7	Yes	T44,T45,T7	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T44,T45,T7	Yes	T44,T45,T7	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T44,T45,T7	Yes	T44,T45,T7	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T44,T45,T7	Yes	T44,T45,T7	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T261,*T454,*T77	Yes	T261,T454,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T44,T45,T7	Yes	T44,T45,T7	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T44,T45,T7	Yes	T44,T45,T7	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T186,T77,T303	Yes	T186,T77,T303	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T42,T43	Yes	T44,T45,T7	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T7,T42,T43	Yes	T44,T45,T7	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T77,*T73,*T74	Yes	T261,T454,T77	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T98,*T186,*T185	Yes	T98,T186,T185	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T44,T45,T7	Yes	T44,T45,T7	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T45,T5	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range