Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3544828	1			T70	616		T71	982		T72	976
values[2]	738354	1			T71	227		T72	301		T122	549
values[3]	112016	1			T72	2		T122	9		T254	1
values[4]	58972	1			T256	24		T554	160		T555	19
values[5]	39339	1			T256	13		T554	178		T555	19
values[6]	28934	1			T256	11		T554	156		T555	19
values[7]	23075	1			T256	9		T554	186		T555	19
values[8]	19587	1			T256	4		T554	140		T555	19
values[9]	17487	1			T256	2		T554	158		T555	19
values[10]	15339	1			T256	3		T554	162		T555	19
values[11]	14153	1			T554	171		T555	20		T565	25
values[12]	13150	1			T554	153		T555	19		T565	28
values[13]	12443	1			T554	151		T555	19		T565	39
values[14]	12031	1			T554	176		T555	21		T565	27
values[15]	11497	1			T554	154		T555	19		T565	34
values[16]	10898	1			T554	138		T555	19		T565	45
values[17]	10223	1			T554	147		T555	19		T565	39
values[18]	10097	1			T554	135		T555	20		T565	33
values[19]	10169	1			T554	144		T555	19		T565	17
values[20]	9319	1			T554	106		T555	19		T565	18
values[21]	9189	1			T554	117		T555	19		T565	29
values[22]	9004	1			T554	80		T555	19		T565	34
values[23]	8556	1			T554	76		T555	19		T565	26
values[24]	8319	1			T554	119		T555	19		T565	46
values[25]	7944	1			T554	150		T555	19		T565	47
values[26]	7993	1			T554	112		T555	19		T565	26
values[27]	7617	1			T554	108		T555	20		T565	21
values[28]	7196	1			T554	90		T555	19		T565	15
values[29]	6494	1			T554	57		T555	20		T565	21
values[30]	6044	1			T554	58		T555	19		T565	5
values[31]	5658	1			T554	54		T555	21		T565	6
values[32]	5273	1			T554	71		T555	19		T565	24
values[33]	4829	1			T554	35		T555	19		T565	20
values[34]	4478	1			T554	40		T555	19		T565	24
values[35]	4231	1			T554	27		T555	19		T565	25
values[36]	4045	1			T554	19		T555	20		T565	11
values[37]	4032	1			T554	17		T555	19		T565	3
values[38]	3772	1			T554	18		T555	19		T565	6
values[39]	3691	1			T554	19		T555	19		T565	5
values[40]	3595	1			T554	18		T555	19		T566	20
values[41]	3424	1			T554	19		T555	20		T566	20
values[42]	3399	1			T554	26		T555	19		T566	21
values[43]	3466	1			T554	18		T555	20		T566	20
values[44]	3354	1			T554	23		T555	20		T566	20
values[45]	3351	1			T554	24		T555	20		T566	20
values[46]	3104	1			T554	14		T555	19		T566	20
values[47]	3178	1			T554	6		T555	19		T566	22
values[48]	3030	1			T554	7		T555	19		T566	20
values[49]	3051	1			T554	11		T555	19		T566	20
values[50]	2931	1			T554	8		T555	19		T566	21
values[51]	2963	1			T554	11		T555	19		T566	21
values[52]	2910	1			T554	10		T555	20		T566	20
values[53]	2901	1			T554	9		T555	20		T566	20
values[54]	2836	1			T554	3		T555	21		T566	20
values[55]	2790	1			T554	1		T555	20		T566	21
values[56]	2699	1			T554	2		T555	19		T566	21
values[57]	2739	1			T554	2		T555	19		T566	20
values[58]	2685	1			T554	2		T555	19		T566	20
values[59]	2675	1			T554	1		T555	19		T566	20
values[60]	2714	1			T554	1		T555	19		T566	20
values[61]	2945	1			T554	1		T555	19		T566	20
values[62]	4370	1			T554	1		T555	19		T566	21
values[63]	11688	1			T554	6		T555	20		T566	21
values[64]	254879	1			T554	172		T555	3534		T566	3484

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4599913	1			T70	630		T71	957		T72	1102
values[2]	801850	1			T71	246		T72	306		T122	537
values[3]	87226	1			T71	4		T72	3		T122	77
values[4]	15535	1			T122	4		T254	2		T256	2
values[5]	5760	1			T122	1		T554	4		T555	27
values[6]	3483	1			T554	1		T555	10		T566	10
values[7]	2401	1			T554	1		T555	3		T566	3
values[8]	2115	1			T554	2		T555	2		T566	3
values[9]	1967	1			T554	1		T555	2		T566	3
values[10]	1755	1			T554	1		T555	2		T566	3
values[11]	1567	1			T554	1		T555	2		T566	3
values[12]	1403	1			T554	1		T555	2		T566	3
values[13]	1354	1			T554	3		T555	2		T566	3
values[14]	1271	1			T554	1		T555	2		T566	3
values[15]	1238	1			T554	5		T555	2		T566	3
values[16]	1222	1			T554	1		T555	2		T566	3
values[17]	1079	1			T554	1		T555	2		T566	3
values[18]	951	1			T554	1		T555	2		T566	3
values[19]	980	1			T554	1		T555	2		T566	3
values[20]	950	1			T554	2		T555	2		T566	3
values[21]	887	1			T554	1		T555	2		T566	3
values[22]	848	1			T554	6		T555	2		T566	3
values[23]	855	1			T554	3		T555	2		T566	3
values[24]	817	1			T554	1		T555	2		T566	3
values[25]	807	1			T554	2		T555	2		T566	3
values[26]	747	1			T554	1		T555	2		T566	3
values[27]	690	1			T554	2		T555	2		T566	4
values[28]	652	1			T554	2		T555	2		T566	3
values[29]	602	1			T554	1		T555	2		T566	3
values[30]	619	1			T554	1		T555	2		T566	4
values[31]	603	1			T554	1		T555	2		T566	3
values[32]	627	1			T554	2		T555	2		T566	3
values[33]	642	1			T554	2		T555	2		T566	3
values[34]	592	1			T554	2		T555	2		T566	3
values[35]	578	1			T554	1		T555	2		T566	3
values[36]	528	1			T554	1		T555	2		T566	3
values[37]	540	1			T554	1		T555	2		T566	3
values[38]	502	1			T554	3		T555	2		T566	3
values[39]	511	1			T554	2		T555	2		T566	3
values[40]	512	1			T554	1		T555	2		T566	3
values[41]	494	1			T554	1		T555	2		T566	3
values[42]	480	1			T554	3		T555	2		T566	3
values[43]	496	1			T554	4		T555	2		T566	3
values[44]	484	1			T554	2		T555	2		T566	4
values[45]	485	1			T554	4		T555	2		T566	3
values[46]	505	1			T554	2		T555	2		T566	3
values[47]	534	1			T554	3		T555	2		T566	3
values[48]	484	1			T554	5		T555	2		T566	3
values[49]	441	1			T554	3		T555	2		T566	3
values[50]	414	1			T554	1		T555	2		T566	3
values[51]	420	1			T554	1		T555	2		T566	3
values[52]	443	1			T554	1		T555	2		T566	3
values[53]	405	1			T554	2		T555	2		T566	3
values[54]	406	1			T554	5		T555	2		T566	3
values[55]	403	1			T554	2		T555	2		T566	3
values[56]	400	1			T554	1		T555	2		T566	3
values[57]	370	1			T554	1		T555	2		T566	3
values[58]	390	1			T554	3		T555	2		T566	3
values[59]	429	1			T554	3		T555	2		T566	3
values[60]	391	1			T554	1		T555	3		T566	3
values[61]	432	1			T554	1		T555	2		T566	3
values[62]	750	1			T554	2		T555	2		T566	3
values[63]	2742	1			T554	8		T555	3		T566	3
values[64]	27488	1			T554	103		T555	290		T566	550

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	524889	1			T70	588		T71	9		T72	9
values[2]	2519595	1			T71	968		T72	1033		T122	1930
values[3]	1154183	1			T71	266		T72	268		T122	685
values[4]	160765	1			T71	1		T72	1		T122	15
values[5]	83144	1			T256	2		T255	1		T560	1
values[6]	52926	1			T554	167		T555	20		T565	15
values[7]	37889	1			T554	152		T555	19		T565	18
values[8]	29330	1			T554	158		T555	21		T565	30
values[9]	23918	1			T554	170		T555	19		T565	48
values[10]	21216	1			T554	208		T555	19		T565	51
values[11]	19005	1			T554	180		T555	19		T565	50
values[12]	17175	1			T554	130		T555	19		T565	34
values[13]	16434	1			T554	138		T555	19		T565	42
values[14]	14955	1			T554	129		T555	20		T565	31
values[15]	14021	1			T554	144		T555	19		T565	27
values[16]	13051	1			T554	176		T555	20		T565	29
values[17]	12807	1			T554	172		T555	19		T565	31
values[18]	12345	1			T554	188		T555	19		T565	65
values[19]	11802	1			T554	144		T555	19		T565	70
values[20]	11451	1			T554	116		T555	19		T565	14
values[21]	11119	1			T554	154		T555	19		T565	19
values[22]	10495	1			T554	191		T555	19		T565	21
values[23]	9830	1			T554	167		T555	19		T565	13
values[24]	9405	1			T554	111		T555	19		T565	9
values[25]	9261	1			T554	103		T555	20		T565	17
values[26]	8656	1			T554	115		T555	19		T565	27
values[27]	8117	1			T554	88		T555	19		T565	29
values[28]	7807	1			T554	62		T555	19		T565	31
values[29]	7287	1			T554	82		T555	19		T565	40
values[30]	6872	1			T554	60		T555	20		T565	35
values[31]	6375	1			T554	50		T555	19		T565	22
values[32]	6011	1			T554	36		T555	19		T565	10
values[33]	5800	1			T554	50		T555	19		T565	7
values[34]	5294	1			T554	36		T555	19		T565	14
values[35]	4919	1			T554	39		T555	19		T565	10
values[36]	4565	1			T554	41		T555	19		T565	11
values[37]	4497	1			T554	30		T555	20		T565	21
values[38]	4221	1			T554	27		T555	19		T565	16
values[39]	4083	1			T554	28		T555	19		T565	9
values[40]	4080	1			T554	26		T555	19		T565	6
values[41]	3862	1			T554	27		T555	20		T565	5
values[42]	3818	1			T554	13		T555	19		T565	1
values[43]	3848	1			T554	33		T555	20		T565	1
values[44]	3585	1			T554	18		T555	19		T565	1
values[45]	3568	1			T554	14		T555	19		T565	1
values[46]	3440	1			T554	14		T555	19		T566	20
values[47]	3398	1			T554	12		T555	19		T566	20
values[48]	3461	1			T554	11		T555	19		T566	20
values[49]	3468	1			T554	8		T555	19		T566	20
values[50]	3357	1			T554	11		T555	20		T566	20
values[51]	3339	1			T554	16		T555	19		T566	20
values[52]	3272	1			T554	8		T555	19		T566	20
values[53]	3262	1			T554	9		T555	19		T566	20
values[54]	3048	1			T554	7		T555	19		T566	20
values[55]	3094	1			T554	8		T555	19		T566	21
values[56]	2998	1			T554	7		T555	19		T566	20
values[57]	3063	1			T554	4		T555	19		T566	21
values[58]	2944	1			T554	5		T555	19		T566	20
values[59]	2856	1			T554	3		T555	21		T566	21
values[60]	2816	1			T554	5		T555	19		T566	20
values[61]	3053	1			T554	4		T555	19		T566	20
values[62]	4031	1			T554	2		T555	19		T566	21
values[63]	10310	1			T554	1		T555	19		T566	21
values[64]	246707	1			T554	102		T555	3655		T566	3673