Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1746051	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36950187

1

T1

6117

T2

6736

T3

17386

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27171341	1			T1	2597		T2	1544		T3	8363
values[0x0]	10176635	1			T1	3520		T2	5192		T3	9023
values[0x1]	1348262	1			T1	366		T2	209		T3	1504

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	536985	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38159253

1

T1

6483

T2

6945

T3

18890

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18348488	1			T1	3242		T2	3473		T3	9446
valid_sources[0x01]	18347799	1			T1	3241		T2	3472		T3	9444
valid_sources[0x02]	32411	1			T203	1		T123	843		T140	239
valid_sources[0x03]	32387	1			T203	1		T123	831		T140	251
valid_sources[0x04]	31940	1			T45	1		T123	913		T140	283
valid_sources[0x05]	35227	1			T65	1		T74	1		T203	1
valid_sources[0x06]	32178	1			T45	3		T123	972		T140	242
valid_sources[0x07]	31822	1			T203	1		T204	5		T123	783
valid_sources[0x08]	32157	1			T74	4		T123	827		T140	241
valid_sources[0x09]	32609	1			T65	1		T123	823		T140	279
valid_sources[0x0a]	31696	1			T65	1		T203	2		T123	746
valid_sources[0x0b]	32611	1			T123	786		T140	271		T760	228
valid_sources[0x0c]	31965	1			T203	1		T123	731		T140	248
valid_sources[0x0d]	32293	1			T65	1		T45	1		T123	849
valid_sources[0x0e]	31877	1			T203	1		T123	856		T140	263
valid_sources[0x0f]	32404	1			T123	739		T140	254		T760	201
valid_sources[0x10]	32507	1			T123	774		T140	262		T760	261
valid_sources[0x11]	32781	1			T123	880		T140	267		T760	222
valid_sources[0x12]	31843	1			T74	7		T204	1		T123	792
valid_sources[0x13]	32094	1			T65	1		T123	800		T140	261
valid_sources[0x14]	32250	1			T65	1		T45	4		T204	12
valid_sources[0x15]	32236	1			T74	1		T203	1		T123	788
valid_sources[0x16]	31696	1			T65	4		T74	7		T203	1
valid_sources[0x17]	31824	1			T65	1		T203	1		T123	735
valid_sources[0x18]	31674	1			T65	1		T74	1		T123	790
valid_sources[0x19]	32128	1			T123	786		T140	255		T760	225
valid_sources[0x1a]	32511	1			T65	1		T45	2		T123	928
valid_sources[0x1b]	31830	1			T65	1		T204	4		T123	849
valid_sources[0x1c]	32586	1			T45	2		T203	1		T123	706
valid_sources[0x1d]	32267	1			T45	1		T123	796		T140	259
valid_sources[0x1e]	31848	1			T65	1		T123	800		T140	282
valid_sources[0x1f]	32095	1			T203	3		T123	739		T140	270
valid_sources[0x20]	32154	1			T65	1		T45	2		T123	812

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26587444

1

T1

2597

T2

1544

T3

8363

values[0x0]

all_enables

biggest_size

10128819

1

T1

3520

T2

5192

T3

9023

values[0x1]

all_enables

biggest_size

233924

1

T65

22

T45

22

T74

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2895036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

457542

1

T70

75

T71

4

T72

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1131907	1			T70	199		T71	26		T72	23
values[0x0]	1084431	1			T70	192		T71	1		T72	7
values[0x1]	1136240	1			T70	225		T71	20		T72	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2243991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1108587

1

T70

191

T71

18

T72

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52676	1			T71	3		T122	30		T462	37
valid_sources[0x01]	51859	1			T71	1		T72	1		T122	32
valid_sources[0x02]	52330	1			T122	42		T462	16		T254	1
valid_sources[0x03]	52515	1			T70	44		T122	42		T462	22
valid_sources[0x04]	51927	1			T71	2		T72	1		T122	38
valid_sources[0x05]	51842	1			T71	1		T122	38		T462	37
valid_sources[0x06]	52601	1			T72	1		T122	33		T462	31
valid_sources[0x07]	52172	1			T71	4		T122	47		T462	29
valid_sources[0x08]	52502	1			T71	1		T122	39		T462	35
valid_sources[0x09]	52019	1			T71	1		T72	1		T122	46
valid_sources[0x0a]	53240	1			T70	11		T122	38		T462	22
valid_sources[0x0b]	52930	1			T70	18		T71	1		T72	1
valid_sources[0x0c]	52367	1			T70	6		T72	3		T122	40
valid_sources[0x0d]	53192	1			T71	1		T72	1		T122	32
valid_sources[0x0e]	52288	1			T70	18		T72	1		T122	46
valid_sources[0x0f]	52750	1			T122	42		T462	29		T254	11
valid_sources[0x10]	53132	1			T70	26		T71	1		T72	1
valid_sources[0x11]	51915	1			T72	1		T122	33		T462	26
valid_sources[0x12]	52621	1			T70	18		T71	1		T72	5
valid_sources[0x13]	52972	1			T72	1		T122	37		T462	21
valid_sources[0x14]	51308	1			T70	7		T71	1		T72	1
valid_sources[0x15]	53104	1			T70	19		T71	2		T72	2
valid_sources[0x16]	51517	1			T122	43		T462	32		T254	1
valid_sources[0x17]	53058	1			T70	5		T72	1		T122	33
valid_sources[0x18]	52222	1			T70	40		T72	2		T122	46
valid_sources[0x19]	52373	1			T70	20		T72	4		T122	30
valid_sources[0x1a]	52034	1			T72	1		T122	42		T462	24
valid_sources[0x1b]	51470	1			T70	34		T71	1		T72	3
valid_sources[0x1c]	52738	1			T71	3		T72	1		T122	44
valid_sources[0x1d]	53592	1			T71	2		T72	2		T122	45
valid_sources[0x1e]	51869	1			T70	10		T122	38		T462	25
valid_sources[0x1f]	52429	1			T70	16		T71	1		T122	43
valid_sources[0x20]	51921	1			T71	1		T122	33		T462	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47959

1

T70

7

T71

2

T122

36

values[0x0]

all_enables

biggest_size

361769

1

T70

61

T71

1

T72

4

values[0x1]

all_enables

biggest_size

47814

1

T70

7

T71

1

T72

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3089748	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

503170

1

T70

77

T71

6

T72

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1228959	1			T70	231		T71	15		T72	34
values[0x0]	1134807	1			T70	195		T71	3		T72	3
values[0x1]	1229152	1			T70	204		T71	28		T72	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2371957	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1220961

1

T70

218

T71

19

T72

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54744	1			T71	2		T122	47		T462	23
valid_sources[0x01]	55532	1			T71	1		T72	1		T122	22
valid_sources[0x02]	56975	1			T71	1		T122	54		T462	16
valid_sources[0x03]	55899	1			T70	35		T72	1		T122	43
valid_sources[0x04]	55798	1			T72	3		T122	55		T462	27
valid_sources[0x05]	56313	1			T71	1		T72	1		T122	64
valid_sources[0x06]	55920	1			T71	1		T72	1		T122	35
valid_sources[0x07]	55674	1			T71	2		T72	1		T122	24
valid_sources[0x08]	56508	1			T71	1		T72	2		T122	38
valid_sources[0x09]	56639	1			T72	2		T122	30		T462	27
valid_sources[0x0a]	56422	1			T70	6		T122	26		T462	21
valid_sources[0x0b]	56054	1			T70	37		T72	1		T122	52
valid_sources[0x0c]	56284	1			T70	17		T72	1		T122	29
valid_sources[0x0d]	55976	1			T72	1		T122	60		T462	24
valid_sources[0x0e]	55937	1			T70	12		T122	40		T462	24
valid_sources[0x0f]	56077	1			T72	1		T122	45		T462	35
valid_sources[0x10]	56256	1			T70	23		T122	67		T462	25
valid_sources[0x11]	56408	1			T71	2		T72	1		T122	45
valid_sources[0x12]	56501	1			T70	13		T122	62		T462	38
valid_sources[0x13]	57678	1			T72	1		T122	40		T462	37
valid_sources[0x14]	55189	1			T70	20		T122	36		T462	41
valid_sources[0x15]	56308	1			T70	16		T71	2		T122	28
valid_sources[0x16]	56705	1			T72	1		T122	42		T462	24
valid_sources[0x17]	56309	1			T70	9		T72	1		T122	35
valid_sources[0x18]	55962	1			T70	34		T71	2		T122	58
valid_sources[0x19]	56240	1			T70	11		T71	1		T72	1
valid_sources[0x1a]	56485	1			T71	1		T122	47		T462	49
valid_sources[0x1b]	56473	1			T70	21		T71	1		T122	40
valid_sources[0x1c]	56415	1			T122	63		T462	19		T254	2
valid_sources[0x1d]	55626	1			T72	2		T122	25		T462	21
valid_sources[0x1e]	56655	1			T70	5		T71	1		T122	54
valid_sources[0x1f]	55764	1			T70	31		T72	4		T122	35
valid_sources[0x20]	55932	1			T72	2		T122	48		T462	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52702

1

T70

7

T71

2

T72

2

values[0x0]

all_enables

biggest_size

398027

1

T70

66

T71

1

T72

1

values[0x1]

all_enables

biggest_size

52441

1

T70

4

T71

3

T72

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2922310	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

461407

1

T70

87

T71

9

T72

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1145783	1			T70	173		T71	22		T72	26
values[0x0]	1094067	1			T70	213		T71	4		T72	2
values[0x1]	1143867	1			T70	202		T71	31		T72	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2263882	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1119835

1

T70

196

T71

24

T72

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52572	1			T71	2		T72	2		T122	42
valid_sources[0x01]	53058	1			T71	1		T122	33		T462	6
valid_sources[0x02]	53490	1			T72	2		T122	29		T462	43
valid_sources[0x03]	53010	1			T70	50		T72	1		T122	39
valid_sources[0x04]	53077	1			T72	1		T122	25		T462	43
valid_sources[0x05]	53216	1			T72	1		T122	23		T462	45
valid_sources[0x06]	52837	1			T72	2		T122	35		T462	15
valid_sources[0x07]	52559	1			T71	2		T122	65		T462	24
valid_sources[0x08]	53247	1			T122	17		T462	4		T254	1
valid_sources[0x09]	52269	1			T122	23		T462	26		T254	14
valid_sources[0x0a]	53734	1			T70	6		T71	1		T72	1
valid_sources[0x0b]	52802	1			T70	32		T71	1		T122	22
valid_sources[0x0c]	52441	1			T70	13		T122	39		T254	13
valid_sources[0x0d]	53337	1			T71	1		T72	1		T122	51
valid_sources[0x0e]	52833	1			T70	17		T72	5		T122	34
valid_sources[0x0f]	52594	1			T71	1		T122	49		T462	2
valid_sources[0x10]	53792	1			T70	19		T71	1		T122	57
valid_sources[0x11]	52725	1			T71	2		T72	1		T122	38
valid_sources[0x12]	53517	1			T70	10		T122	44		T462	88
valid_sources[0x13]	53035	1			T71	2		T72	3		T122	78
valid_sources[0x14]	52868	1			T70	18		T71	1		T122	38
valid_sources[0x15]	53214	1			T70	7		T71	1		T122	73
valid_sources[0x16]	53658	1			T71	2		T72	1		T122	36
valid_sources[0x17]	52692	1			T70	5		T71	1		T122	24
valid_sources[0x18]	52840	1			T70	35		T71	1		T122	43
valid_sources[0x19]	52322	1			T70	6		T122	45		T462	25
valid_sources[0x1a]	53022	1			T122	25		T462	41		T256	2
valid_sources[0x1b]	52716	1			T70	25		T71	4		T72	2
valid_sources[0x1c]	52823	1			T72	2		T122	40		T462	21
valid_sources[0x1d]	53418	1			T72	3		T122	55		T462	11
valid_sources[0x1e]	52946	1			T70	16		T71	4		T122	46
valid_sources[0x1f]	51830	1			T70	27		T72	1		T122	20
valid_sources[0x20]	52248	1			T72	2		T122	23		T462	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48444

1

T70

11

T71

3

T72

2

values[0x0]

all_enables

biggest_size

365016

1

T70

60

T71

1

T122

301

values[0x1]

all_enables

biggest_size

47947

1

T70

16

T71

5

T72

4