Toggle Coverage for Module :
uart
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
308 |
308 |
100.00 |
Total Bits 0->1 |
154 |
154 |
100.00 |
Total Bits 1->0 |
154 |
154 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
308 |
308 |
100.00 |
Port Bits 0->1 |
154 |
154 |
100.00 |
Port Bits 1->0 |
154 |
154 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T2,T3,T6 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T8,T114,T115 |
Yes |
T8,T114,T115 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T8,T114,T115 |
Yes |
T8,T114,T115 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T70,*T71,*T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_address[15:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17:16] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[29:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T73,*T65,*T45 |
Yes |
T73,T65,T45 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T65,T45,T74 |
Yes |
T65,T45,T74 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T8,T114,T115 |
Yes |
T8,T114,T115 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T8,T114,T115 |
Yes |
T8,T114,T115 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T8,T114,T115 |
Yes |
T8,T114,T115 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T8,T114,T115 |
Yes |
T8,T114,T115 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T8,T114,T115 |
Yes |
T8,T114,T115 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T762,*T767,*T70 |
Yes |
T762,T767,T70 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T8,*T114,*T115 |
Yes |
T8,T114,T115 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T8,T114,T115 |
Yes |
T8,T114,T115 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T331,T75,T149 |
Yes |
T331,T75,T149 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T331,T75,T149 |
Yes |
T75,T149,T153 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T75,T149,T153 |
Yes |
T331,T75,T149 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T331,T75,T149 |
Yes |
T331,T75,T149 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T2,T3,T6 |
Yes |
T1,T2,T3 |
INPUT |
cio_tx_o |
Yes |
Yes |
T8,T114,T115 |
Yes |
T8,T114,T115 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T114,T115,T142 |
Yes |
T114,T115,T142 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T114,T115,T142 |
Yes |
T114,T115,T142 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T114,T115,T142 |
Yes |
T114,T115,T142 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T114,T115,T142 |
Yes |
T114,T115,T142 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T114,T115,T142 |
Yes |
T114,T115,T142 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
304 |
304 |
100.00 |
Total Bits 0->1 |
152 |
152 |
100.00 |
Total Bits 1->0 |
152 |
152 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
304 |
304 |
100.00 |
Port Bits 0->1 |
152 |
152 |
100.00 |
Port Bits 1->0 |
152 |
152 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T2,T3,T6 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T8,T115,T42 |
Yes |
T8,T115,T42 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T8,T115,T42 |
Yes |
T8,T115,T42 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T70,*T71,*T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_address[29:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T73,*T65,*T45 |
Yes |
T73,T65,T45 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T65,T45,T74 |
Yes |
T65,T45,T74 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T8,T115,T42 |
Yes |
T8,T115,T42 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T8,T115,T42 |
Yes |
T8,T115,T42 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T8,T115,T42 |
Yes |
T8,T115,T42 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T8,T115,T42 |
Yes |
T8,T115,T42 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T8,T115,T42 |
Yes |
T8,T115,T42 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T762,*T767,*T70 |
Yes |
T762,T767,T70 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T8,*T115,*T42 |
Yes |
T8,T115,T42 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T8,T115,T42 |
Yes |
T8,T115,T42 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T75,T149,T365 |
Yes |
T75,T149,T365 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T75,T153,T76 |
Yes |
T75,T153,T77 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T75,T153,T77 |
Yes |
T75,T153,T76 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T75,T149,T365 |
Yes |
T75,T149,T365 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T2,T3,T6 |
Yes |
T1,T2,T3 |
INPUT |
cio_tx_o |
Yes |
Yes |
T8,T115,T42 |
Yes |
T8,T115,T42 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T115,T324,T407 |
Yes |
T115,T324,T407 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T115,T324,T326 |
Yes |
T115,T324,T326 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T115,T324,T326 |
Yes |
T115,T324,T326 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T115,T324,T339 |
Yes |
T115,T324,T339 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T115,T324,T339 |
Yes |
T115,T324,T339 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
306 |
306 |
100.00 |
Total Bits 0->1 |
153 |
153 |
100.00 |
Total Bits 1->0 |
153 |
153 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
306 |
306 |
100.00 |
Port Bits 0->1 |
153 |
153 |
100.00 |
Port Bits 1->0 |
153 |
153 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T2,T3,T6 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T324,T326,T216 |
Yes |
T324,T326,T216 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T324,T326,T216 |
Yes |
T324,T326,T216 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T70,*T71,*T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_address[15:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[16] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[29:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T73,*T65,*T45 |
Yes |
T73,T65,T45 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T65,T45,T74 |
Yes |
T65,T45,T74 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T149,T324,T326 |
Yes |
T149,T324,T326 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T149,T324,T326 |
Yes |
T149,T324,T326 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T324,T326,T216 |
Yes |
T324,T326,T216 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T149,T324,T326 |
Yes |
T149,T324,T326 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T149,T324,T326 |
Yes |
T149,T324,T326 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T70,*T71,*T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T324,*T326,*T216 |
Yes |
T324,T326,T216 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T149,T324,T326 |
Yes |
T149,T324,T326 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T331,T75,T149 |
Yes |
T331,T75,T149 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T331,T75,T156 |
Yes |
T75,T156,T77 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T75,T156,T77 |
Yes |
T331,T75,T156 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T331,T75,T149 |
Yes |
T331,T75,T149 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T216,T340,T372 |
Yes |
T216,T9,T12 |
INPUT |
cio_tx_o |
Yes |
Yes |
T216,T340,T372 |
Yes |
T216,T340,T372 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T324,T326,T216 |
Yes |
T324,T326,T216 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T324,T326,T216 |
Yes |
T324,T326,T216 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T324,T326,T216 |
Yes |
T324,T326,T216 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T324,T326,T216 |
Yes |
T324,T326,T216 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T324,T326,T216 |
Yes |
T324,T326,T216 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
306 |
306 |
100.00 |
Total Bits 0->1 |
153 |
153 |
100.00 |
Total Bits 1->0 |
153 |
153 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
306 |
306 |
100.00 |
Port Bits 0->1 |
153 |
153 |
100.00 |
Port Bits 1->0 |
153 |
153 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T2,T3,T6 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T114,T142,T324 |
Yes |
T114,T142,T324 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T114,T142,T324 |
Yes |
T114,T142,T324 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T70,*T71,*T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_address[16:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[29:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T73,*T65,*T45 |
Yes |
T73,T65,T45 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T65,T45,T74 |
Yes |
T65,T45,T74 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T114,T142,T149 |
Yes |
T114,T142,T149 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T114,T142,T149 |
Yes |
T114,T142,T149 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T114,T142,T324 |
Yes |
T114,T142,T324 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T114,T142,T149 |
Yes |
T114,T142,T149 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T114,T142,T149 |
Yes |
T114,T142,T149 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T70,*T71,*T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T114,*T142,*T324 |
Yes |
T114,T142,T324 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T114,T142,T149 |
Yes |
T114,T142,T149 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T75,T149,T157 |
Yes |
T75,T149,T157 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T75,T149,T153 |
Yes |
T75,T149,T153 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T75,T149,T153 |
Yes |
T75,T149,T153 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T75,T149,T157 |
Yes |
T75,T149,T157 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T114,T142,T334 |
Yes |
T114,T142,T334 |
INPUT |
cio_tx_o |
Yes |
Yes |
T114,T142,T334 |
Yes |
T114,T142,T334 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T114,T142,T324 |
Yes |
T114,T142,T324 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T114,T142,T324 |
Yes |
T114,T142,T324 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T114,T142,T324 |
Yes |
T114,T142,T324 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T114,T142,T324 |
Yes |
T114,T142,T324 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T114,T142,T324 |
Yes |
T114,T142,T324 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
308 |
308 |
100.00 |
Total Bits 0->1 |
154 |
154 |
100.00 |
Total Bits 1->0 |
154 |
154 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
308 |
308 |
100.00 |
Port Bits 0->1 |
154 |
154 |
100.00 |
Port Bits 1->0 |
154 |
154 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T2,T3,T6 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T4,T5,T324 |
Yes |
T4,T5,T324 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T4,T5,T324 |
Yes |
T4,T5,T324 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T70,*T71,*T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_address[15:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17:16] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[29:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T73,*T65,*T45 |
Yes |
T73,T65,T45 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T65,T45,T74 |
Yes |
T65,T45,T74 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T4,T5,T149 |
Yes |
T4,T5,T149 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T4,T5,T149 |
Yes |
T4,T5,T149 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T4,T5,T324 |
Yes |
T4,T5,T324 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T4,T5,T149 |
Yes |
T4,T5,T149 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T4,T5,T149 |
Yes |
T4,T5,T149 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T70,*T71,*T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T70,T71,T72 |
Yes |
T70,T71,T72 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T4,*T5,*T324 |
Yes |
T4,T5,T324 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T4,T5,T149 |
Yes |
T4,T5,T149 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T75,T149,T768 |
Yes |
T75,T149,T768 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T75,T156,T87 |
Yes |
T75,T156,T77 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T75,T156,T77 |
Yes |
T75,T156,T87 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T75,T149,T768 |
Yes |
T75,T149,T768 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T4,T5,T364 |
Yes |
T4,T5,T364 |
INPUT |
cio_tx_o |
Yes |
Yes |
T4,T5,T364 |
Yes |
T4,T5,T364 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T4,T5,T324 |
Yes |
T4,T5,T324 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T4,T5,T324 |
Yes |
T4,T5,T324 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T4,T5,T324 |
Yes |
T4,T5,T324 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T4,T5,T324 |
Yes |
T4,T5,T324 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T4,T5,T324 |
Yes |
T4,T5,T324 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T324,T326,T337 |
Yes |
T324,T326,T337 |
OUTPUT |
*Tests covering at least one bit in the range