Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	1044153304	4452	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	1044153304	4452	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	4452	0	0
T1	422903	1	0	0
T2	128237	2	0	0
T3	278856	4	0	0
T4	757334	2	0	0
T5	654157	1	0	0
T6	249735	3	0	0
T7	55998	0	0	0
T8	155511	25	0	0
T43	0	2	0	0
T80	208016	2	0	0
T81	162624	1	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	8	0	0
T180	0	12	0	0
T182	0	8	0	0
T234	994262	0	0	0
T309	0	3	0	0
T310	0	8	0	0
T311	0	9	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	4452	0	0
T1	422903	1	0	0
T2	128237	2	0	0
T3	278856	4	0	0
T4	757334	2	0	0
T5	654157	1	0	0
T6	249735	3	0	0
T7	55998	0	0	0
T8	155511	25	0	0
T43	0	2	0	0
T80	208016	2	0	0
T81	162624	1	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	8	0	0
T180	0	12	0	0
T182	0	8	0	0
T234	994262	0	0	0
T309	0	3	0	0
T310	0	8	0	0
T311	0	9	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	522076652	48	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	522076652	48	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	48	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	8	0	0
T180	0	12	0	0
T182	0	8	0	0
T234	994262	0	0	0
T309	0	3	0	0
T310	0	8	0	0
T311	0	9	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	48	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	8	0	0
T180	0	12	0	0
T182	0	8	0	0
T234	994262	0	0	0
T309	0	3	0	0
T310	0	8	0	0
T311	0	9	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	522076652	4404	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	522076652	4404	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	4404	0	0
T1	422903	1	0	0
T2	128237	2	0	0
T3	278856	4	0	0
T4	757334	2	0	0
T5	654157	1	0	0
T6	249735	3	0	0
T7	55998	0	0	0
T8	155511	25	0	0
T43	0	2	0	0
T80	208016	2	0	0
T81	162624	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	4404	0	0
T1	422903	1	0	0
T2	128237	2	0	0
T3	278856	4	0	0
T4	757334	2	0	0
T5	654157	1	0	0
T6	249735	3	0	0
T7	55998	0	0	0
T8	155511	25	0	0
T43	0	2	0	0
T80	208016	2	0	0
T81	162624	1	0	0